reg_caltiming8

         
      
Module Instance Base Address Register Address
iohmc_ctrl_inst_0_iohmc_ctrl_mmr_top_inst 0xF8010000 0xF801009C

Size: 32

Offset: 0x9C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_t_param_mmr_cmd_to_valid

RW 0x0

cfg_t_param_rld3_multibank_ref_delay

RW 0x0

cfg_t_param_mps_exit_cke_to_cs

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_t_param_mps_exit_cke_to_cs

RW 0x0

cfg_t_param_mps_exit_cs_to_cke

RW 0x0

cfg_t_param_mpr_to_valid

RW 0x0

cfg_t_param_mrr_to_valid

RW 0x0

reg_caltiming8 Fields

Bit Name Description Access Reset
27:20 cfg_t_param_mmr_cmd_to_valid
iohmc_ctrl_mmr_top_inst.cfg_t_param_mmr_cmd_to_valid[7:0]
Name:MMR Cmd to Valid Timing
Description:MMR cmd to valid delay.
RW 0x0
19:17 cfg_t_param_rld3_multibank_ref_delay
iohmc_ctrl_mmr_top_inst.cfg_t_param_rld3_multibank_ref_delay[2:0]
Name:Reserved
Description:TBD
RW 0x0
16:13 cfg_t_param_mps_exit_cke_to_cs
iohmc_ctrl_mmr_top_inst.cfg_t_param_mps_exit_cke_to_cs[3:0]
Name:Max Power Saving CKE to CS
Description:Timing parameter for exit Maximum Power Saving. Timing requirement for CKE de-assertion vs CS de-assertion. tMPX_LH.
RW 0x0
12:9 cfg_t_param_mps_exit_cs_to_cke
iohmc_ctrl_mmr_top_inst.cfg_t_param_mps_exit_cs_to_cke[3:0]
Name:Max Power Saving CS to CKE
Description:Timing parameter for exit Maximum Power Saving. Timing requirement for CS assertion vs CKE de-assertion. tMPX_S.
RW 0x0
8:4 cfg_t_param_mpr_to_valid
iohmc_ctrl_mmr_top_inst.cfg_t_param_mpr_to_valid[4:0]
Name:Multi Purpose Register Read to Valid
Description:Timing parameter for Multi Purpose Register Read to any valid command.
RW 0x0
3:0 cfg_t_param_mrr_to_valid
iohmc_ctrl_mmr_top_inst.cfg_t_param_mrr_to_valid[3:0]
Name:Mode Register Read to Valid
Description:Timing parameter for Mode Register Read to any valid command.
RW 0x0