SMMU_CB31_SCTLR

         The System Control register provides the top level control of the translation system for the related Context bank.
      
Note: For register and programming information, please refer to the Arm® CoreLink™ MMU System Memory Management Unit Technical Reference Manual.
Module Instance Base Address Register Address
i_aps_smmu_secure_registers 0xFA000000 0xFA03F000

Size: 32

Offset: 0x3F000

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

NSCFG

RW 0x0

WACFG

RW 0x0

RACFG

RW 0x0

SHCFG

RW 0x0

FB

RW 0x0

MTCFG

RW 0x0

MemAttr

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TRANSIENTCFG

RW 0x0

PTW

RW 0x0

ASIDPNE

RO 0x0

Reserved

UWXN

RW 0x0

WXN

RW 0x0

HUPCF

RW 0x1

CFCFG

RW 0x0

CFIE

RW 0x0

CFRE

RW 0x0

E

RW 0x0

AFFD

RW 0x0

AFE

RW 0x0

TRE

RW 0x0

M

RW 0x0