IC_DMA_RDLR

         Name: I2C Receive Data Level Register
Size: log2(IC_RX_BUFFER_DEPTH)  bits
Address Offset: 0x90
Read/Write Access: Read/Write
This register is only valid when DW_apb_i2c
is configured with a set of DMA interface signals
(IC_HAS_DMA = 1). When DW_apb_i2c is not configured
for DMA operation, this register does not exist;
writing to its address has no effect; reading from
its address returns zero.

Module Instance	Base Address	Register Address
`sdm_i2c_0_DW_apb_i2c_addr_block0`	`0xFF8D0100`	`0xFF8D0190`
`sdm_i2c_1_DW_apb_i2c_addr_block1`	`0xFF8D0200`	`0xFF8D0290`

Size: 32

Offset: 0x90

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RSVD_DMA_RDLR` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RSVD_DMA_RDLR` `RO 0x0`										`DMARDL` `RW 0x0`

IC_DMA_RDLR Fields

Bit	Name	Description	Access	Reset
31:6	`RSVD_DMA_RDLR`	Reserved bits - Read Only	`RO`	`0x0`
5:0	`DMARDL`	Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. Reset value: 0x0	`RW`	`0x0`

Bit

Name

Description

Access

Reset

31:6

RSVD_DMA_RDLR

Reserved bits - Read Only

RO

0x0

5:0

DMARDL

Receive Data Level.
This bit field controls the level at which a DMA
request is made by the receive logic. The watermark level =
DMARDL+1; that is, dma_rx_req is generated when the number
of valid data entries in the receive FIFO is equal to or more
than this field value + 1, and RDMAE =1. For instance, when
DMARDL is 0, then dma_rx_req is asserted when 1 or more data
entries are present in the receive FIFO.
Reset value: 0x0

RW

0x0