HCCHAR6
Host Channel 6 Characteristics Register
Module Instance | Base Address | Register Address |
---|---|---|
i_usbotg_0_DWC_otg_intreg | 0xFFB00000 | 0xFFB005C0 |
i_usbotg_1_DWC_otg_intreg | 0xFFB40000 | 0xFFB405C0 |
Size: 32
Offset: 0x5C0
Access: RW
Bit Fields | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ChEna RW 0x0 |
ChDis RW 0x0 |
OddFrm RW 0x0 |
DevAddr RW 0x0 |
EC RW 0x0 |
EPType RW 0x0 |
LSpdDev RW 0x0 |
RESERVED RO 0x0 |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EPDir RW 0x0 |
EPNum RW 0x0 |
MPS RW 0x0 |
HCCHAR6 Fields
Bit | Name | Description | Access | Reset | ||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | ChEna |
Channel Enable (ChEna) When Scatter/Gather mode is enabled 1'b0: Indicates that the descriptor structure is not yet ready. 1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor. When Scatter/Gather mode is disabled This field is set by the application and cleared by the OTG host. 1'b0: Channel disabled 1'b1: Channel enabled
|
RW | 0x0 | ||||||||||||||||||||||||||||||||||
30 | ChDis |
Channel Disable (ChDis) The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer For that channel is complete. The application must wait For the Channel Disabled interrupt before treating the channel as disabled.
|
RW | 0x0 | ||||||||||||||||||||||||||||||||||
29 | OddFrm |
Odd Frame (OddFrm) This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd (micro)frame. This field is applicable for only periodic (isochronous and interrupt) transactions. 1'b0: Even (micro)frame 1'b1: Odd (micro)frame
|
RW | 0x0 | ||||||||||||||||||||||||||||||||||
28:22 | DevAddr |
Device Address (DevAddr) This field selects the specific device serving as the data source or sink. |
RW | 0x0 | ||||||||||||||||||||||||||||||||||
21:20 | EC |
Multi Count (MC) / Error Count (EC) When the Split Enable bit of the Host Channel-n Split Control register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to the host the number of transactions that must be executed per microframe For this periodic endpoint. For non periodic transfers, this field is used only in DMA mode, and specifies the number packets to be fetched For this channel before the internal DMA engine changes arbitration. 2'b00: Reserved This field yields undefined results. 2'b01: 1 transaction 2'b10: 2 transactions to be issued for this endpoint per microframe 2'b11: 3 transactions to be issued for this endpoint per microframe When HCSPLTn.SpltEna is Set (1'b1), this field indicates the number of immediate retries to be performed For a periodic split transactions on transaction errors. This field must be Set to at least 2'b01.
|
RW | 0x0 | ||||||||||||||||||||||||||||||||||
19:18 | EPType |
Endpoint Type (EPType) Indicates the transfer type selected. 2'b00: Control 2'b01: Isochronous 2'b10: Bulk 2'b11: Interrupt
|
RW | 0x0 | ||||||||||||||||||||||||||||||||||
17 | LSpdDev |
Low-Speed Device (LSpdDev) This field is Set by the application to indicate that this channel is communicating to a low-speed device.
|
RW | 0x0 | ||||||||||||||||||||||||||||||||||
16 | RESERVED |
RESERVED |
RO | 0x0 | ||||||||||||||||||||||||||||||||||
15 | EPDir |
Endpoint Direction (EPDir) Indicates whether the transaction is IN or OUT. 1'b0: OUT 1'b1: IN
|
RW | 0x0 | ||||||||||||||||||||||||||||||||||
14:11 | EPNum |
Endpoint Number (EPNum) Indicates the endpoint number on the device serving as the data source or sink.
|
RW | 0x0 | ||||||||||||||||||||||||||||||||||
10:0 | MPS |
Maximum Packet Size (MPS) Indicates the maximum packet size of the associated endpoint. |
RW | 0x0 |