rxthresh 

         Device Instruction Configuration Register
Module Instance Base Address Register Address
sdm_qspi_qspiregs 0xFF8D2000 0xFF8D2034

Size: 32

Offset: 0x34

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

rx_thresh_resv_fld

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

rx_thresh_resv_fld

RO 0x0

level

RW 0x1

rxthresh Fields

Bit Name Description Access Reset
31:4 rx_thresh_resv_fld 


                     		

                     
                        RO
                     

                     
                        0x0
                     

                  


                  

                     3:0

                     
                        level
                     

                     
                        
 Defines the level at which the small RX FIFO not empty interrupt is generated 


                     		

                     
                        RW
                     

                     
                        0x1