reg_caltiming1

         Calibration Timing 1 Register
      
Module Instance Base Address Register Address
iohmc_ctrl_inst_0_iohmc_ctrl_mmr_top_inst 0xF8010000 0xF8010080

Size: 32

Offset: 0x80

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_t_param_rd_to_wr_diff_chip

RO 0x0

cfg_t_param_rd_to_wr

RO 0x0

cfg_t_param_rd_to_rd_diff_bg

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_t_param_rd_to_rd_diff_bg

RO 0x0

cfg_t_param_rd_to_rd_diff_chip

RO 0x0

cfg_t_param_rd_to_rd

RO 0x0

reg_caltiming1 Fields

Bit Name Description Access Reset
29:24 cfg_t_param_rd_to_wr_diff_chip
iohmc_ctrl_mmr_top_inst.cfg_t_param_rd_to_wr_diff_chip[5:0]
Name:Rd to Wr Diff Chip
Description:Read to write command timing on different chips.
RO 0x0
23:18 cfg_t_param_rd_to_wr
iohmc_ctrl_mmr_top_inst.cfg_t_param_rd_to_wr[5:0]
Name:Rd to Wr Same Bank
Description:Write to read command timing on same bank.
RO 0x0
17:12 cfg_t_param_rd_to_rd_diff_bg
iohmc_ctrl_mmr_top_inst.cfg_t_param_rd_to_rd_diff_bg[5:0]
Name:Rd to Rd Diff Bank Group
Description:Read to read command timing on different bank groups, DDR4 only.
RO 0x0
11:6 cfg_t_param_rd_to_rd_diff_chip
iohmc_ctrl_mmr_top_inst.cfg_t_param_rd_to_rd_diff_chip[5:0]
Name:Rd to Rd Diff Chip
Description:Read to read command timing on different chips.
RO 0x0
5:0 cfg_t_param_rd_to_rd
iohmc_ctrl_mmr_top_inst.cfg_t_param_rd_to_rd[5:0]
Name:Rd to Rd Same Bank
Description:Read to read command timing on same bank.
RO 0x0