global_int_enable 

         Global Interrupt enable and Error/Timeout disable.
Module Instance Base Address Register Address
sdm_i_nand_config 0xFFA10000 0xFFA100F0

Size: 32

Offset: 0xF0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

error_rpt_disable

RW 0x0

Reserved

timeout_disable

RW 0x0

Reserved

flag

RW 0x0

global_int_enable Fields

Bit Name Description Access Reset
8 error_rpt_disable 
Command and ECC uncorrectable failures will not be 
                                                reported when this bit is set
RW 0x0
4 timeout_disable 
Watchdog timer logic will be de-activated when 
                                              this bit is set.
 RW 0x0
0 flag 
Host will receive an interrupt only when this bit is set.
 RW 0x0