IC_CON

         Name: I2C Control Register
Size: 20 bits
Address Offset: 0x00
Read/Write Access:
If configuration parameter  I2C_DYNAMIC_TAR_UPDATE=1 bit 4 is readonly. 
If configuration parameter  IC_RX_FULL_HLD_BUS_EN =0  bit 9 is readonly.
If configuration parameter IC_STOP_DET_IF_MASTER_ACTIVE =0 bit 10 is readonly.
If configuration parameter IC_BUS_CLEAR_FEATURE=0 bit 11 is readonly
If configuration parameter IC_OPTIONAL_SAR=0  bit 16 is readonly
If configuration parameter IC_SMBUS=0  bit 17 is readonly
If configuration parameter IC_SMBUS_ARP=0  bits 18 & 19 are readonly

This register can be written only when the DW_apb_i2c
is disabled, which corresponds to the IC_ENABLE[0] register
being set to 0. Writes at other times have no effect.
      
Module Instance Base Address Register Address
sdm_i2c_0_DW_apb_i2c_addr_block0 0xFF8D0100 0xFF8D0100
sdm_i2c_1_DW_apb_i2c_addr_block1 0xFF8D0200 0xFF8D0200

Size: 32

Offset: 0x0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD_IC_CON_2

RO 0x0

RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN

RO 0x0

RSVD_SMBUS_ARP_EN

RO 0x0

RSVD_SMBUS_SLAVE_QUICK_EN

RO 0x0

RSVD_OPTIONAL_SAR_CTRL

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD_IC_CON_1

RO 0x0

RSVD_BUS_CLEAR_FEATURE_CTRL

RO 0x0

STOP_DET_IF_MASTER_ACTIVE

RO 0x0

RX_FIFO_FULL_HLD_CTRL

RO 0x0

TX_EMPTY_CTRL

RW 0x0

STOP_DET_IFADDRESSED

RW 0x0

IC_SLAVE_DISABLE

RW 0x1

IC_RESTART_EN

RW 0x1

IC_10BITADDR_MASTER_rd_only

RO 0x1

IC_10BITADDR_SLAVE

RW 0x1

SPEED

RW 0x2

MASTER_MODE

RW 0x1

IC_CON Fields

Bit Name Description Access Reset
31:20 RSVD_IC_CON_2
Reserved bits - Read Only
RO 0x0
19 RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN
Reserved bits - Read Only
RO 0x0
18 RSVD_SMBUS_ARP_EN
Reserved bits - Read Only
RO 0x0
17 RSVD_SMBUS_SLAVE_QUICK_EN
Reserved bits - Read Only
RO 0x0
16 RSVD_OPTIONAL_SAR_CTRL
Reserved bits - Read Only
RO 0x0
15:12 RSVD_IC_CON_1
Reserved bits - Read Only
RO 0x0
11 RSVD_BUS_CLEAR_FEATURE_CTRL
Reserved bits - Read Only
RO 0x0
10 STOP_DET_IF_MASTER_ACTIVE
In Master mode:
1'b1: issues the STOP_DET interrupt only when master is active.
1'b0: issues the STOP_DET irrespective of whether master is active or not.
Dependencies: This Register bit value is applicable only when IC_STOP_DET_IF_MASTER_ACTIVE=1 and IC_ULTRA_FAST_MODE=0
Reset value: 0x0.
Value Description
0x0 Master issues the STOP_DET interrupt irrespective of whether master is active or not
0x1 Master issues the STOP_DET interrupt only when master is active
RO 0x0
9 RX_FIFO_FULL_HLD_CTRL
This bit controls whether 
DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH,
as described in the IC_RX_FULL_HLD_BUS_EN parameter. 
Dependencies: This register bit value is applicable only when the
IC_RX_FULL_HLD_BUS_EN configuration parameter is set to 1 and IC_ULTRA_FAST_MODE=0
If IC_RX_FULL_HLD_BUS_EN = 0, then this bit is read-only. 
If IC_RX_FULL_HLD_BUS_EN = 1, then this bit can be read or write.
Reset value: 0x0.
Value Description
0x0 Overflow when RX_FIFO is full
0x1 Hold bus when RX_FIFO is full
RO 0x0
8 TX_EMPTY_CTRL
This bit controls the generation 
of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register.
Reset value: 0x0.
Value Description
0x0 Default behaviour of TX_EMPTY interrupt
0x1 Controlled generation of TX_EMPTY interrupt
RW 0x0
7 STOP_DET_IFADDRESSED
In slave mode:
1:  issues the STOP_DET interrrupt only when it is addressed.
0:  issues the STOP_DET irrespective of whether it's addressed or not.
Dependencies: This register bit value is applicable in the slave mode only (MASTER_MODE = 1'b0)
Reset value: 0x0
NOTE: During a general call address, this slave does not issue the 
STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if
the slave responds to the general call address by generating ACK.
The STOP_DET interrupt is generated only when the transmitted
address matches the slave address (SAR).
Value Description
0x0 slave issues STOP_DET intr always
0x1 slave issues STOP_DET intr only if addressed
RW 0x0
6 IC_SLAVE_DISABLE
This bit controls whether I2C has its slave disabled,
which means once the presetn signal is applied, then
this bit takes on the value of the configuration parameter
IC_SLAVE_DISABLE. You have the choice of having the slave enabled
or disabled after reset is applied, which means software does not
have to configure the slave. By default, the slave is always enabled
(in reset state as well). If you need to disable it after reset, set
this bit to 1.
If this bit is set (slave is disabled), DW_apb_i2c functions only as
a master and does not perform any action that requires a slave.
0: slave is enabled
1: slave is disabled
Reset value: IC_SLAVE_DISABLE configuration parameter
NOTE: Software should ensure that if this bit is written with 0,
then bit 0 should also be written with a 0.
Value Description
0x0 Slave mode is enabled
0x1 Slave mode is disabled
RW 0x1
5 IC_RESTART_EN
Determines whether RESTART conditions may be sent when
acting as a master. Some older slaves do not support handling
RESTART conditions; however, RESTART conditions are used in
several DW_apb_i2c operations.
0: disable
1: enable
When RESTART is disabled, the master is prohibited from
performing the following functions:
- Change direction within a transfer (split)
- Send a START BYTE
- High-speed mode operation
- Combined format transfers in 7-bit addressing modes
- Read operation with a 10-bit address
- Send multiple bytes per transfer
By replacing RESTART condition followed by a STOP and a
subsequent START condition, split operations are broken down
into multiple DW_apb_i2c transfers. If the above operations are
performed, it will result in setting bit 6 (TX_ABRT) of the
IC_RAW_INTR_STAT register.
Reset value: IC_RESTART_EN configuration parameter
Value Description
0x0 Master restart disabled
0x1 Master restart enabled
RW 0x1
4 IC_10BITADDR_MASTER_rd_only
If the I2C_DYNAMIC_TAR_UPDATE configuration parameter is
set to 'No' (0), this bit is named IC_10BITADDR_MASTER and
controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit
addressing mode when acting as a master.
If I2C_DYNAMIC_TAR_UPDATE is set to 'Yes' (1), the
function of this bit is handled by bit 12 of IC_TAR register, and
becomes a read-only copy called
IC_10BITADDR_MASTER_rd_only.
0: 7-bit addressing
1: 10-bit addressing
Dependencies: If I2C_DYNAMIC_TAR_UPDATE = 1, then this
bit is read-only. If I2C_DYNAMIC_TAR_UPDATE = 0, then this
bit can be read or write.
Reset value: IC_10BITADDR_MASTER configuration
parameter
Value Description
0x0 Master 7Bit addressing mode
0x1 Master 10Bit addressing mode
RO 0x1
3 IC_10BITADDR_SLAVE
When acting as a slave, this bit controls whether the DW_apb_i2c
responds to 7- or 10-bit addresses.
0: 7-bit addressing. The DW_apb_i2c ignores transactions that
   involve 10-bit addressing; for 7-bit addressing,
   only the lower 7 bits of the IC_SAR register are compared.
1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit
   addressing transfers that match the full 10 bits of the IC_SAR
   register.
Reset value: IC_10BITADDR_SLAVE configuration parameter
Value Description
0x0 Slave 7Bit addressing
0x1 Slave 10Bit addressing
RW 0x1
2:1 SPEED
These bits control at which speed the DW_apb_i2c operates; its
setting is relevant only if one is operating the DW_apb_i2c in
master mode. Hardware protects against illegal values being
programmed by software. This register should be programmed
only with a value in the range of 1 to IC_MAX_SPEED_MODE;
otherwise, hardware updates this register with the value of
IC_MAX_SPEED_MODE.
1: standard mode (100 kbit/s)
2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s)
3: high speed mode (3.4 Mbit/s)
Dependencies: This field is not applicable  when IC_ULTRA_FAST_MODE=1
Reset value: IC_MAX_SPEED_MODE configuration
Value Description
0x1 Standard Speed mode of operation
0x2 Fast or Fast Plus mode of operation
0x3 High Speed mode of operation
RW 0x2
0 MASTER_MODE
This bit controls whether the DW_apb_i2c master is enabled.
0: master disabled
1: master enabled
Reset value: IC_MASTER_MODE configuration parameter
NOTE: Software should ensure that if this bit is written with '1'
then bit 6 should also be written with a '1'.
Value Description
0x0 Master mode is disabled
0x1 Master mode is enabled
RW 0x1