HCINT6 

         Host Channel 6 Interrupt Register
Module Instance Base Address Register Address
i_usbotg_0_DWC_otg_intreg 0xFFB00000 0xFFB005C8
i_usbotg_1_DWC_otg_intreg 0xFFB40000 0xFFB405C8

Size: 32

Offset: 0x5C8

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED

RO 0x0

DESC_LST_ROLLIntr

RW 0x0

XCS_XACT_ERR

RW 0x0

BNAIntr

RW 0x0

DataTglErr

RW 0x0

FrmOvrun

RW 0x0

BblErr

RW 0x0

XactErr

RW 0x0

NYET

RW 0x0

ACK

RW 0x0

NAK

RW 0x0

STALL

RW 0x0

AHBErr

RW 0x0

ChHltd

RW 0x0

XferCompl

RW 0x0

HCINT6 Fields

Bit Name Description Access Reset
31:14 RESERVED 
RESERVED
 RO 0x0
13 DESC_LST_ROLLIntr 
Descriptor rollover interrupt (DESC_LST_ROLLIntr)
This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit 
when the corresponding channel's descriptor list rolls over.
For non Scatter/Gather DMA mode, this bit is reserved.
Value Description
0x0 No Descriptor rollover interrupt
0x1 Descriptor rollover interrupt
RW 0x0
12 XCS_XACT_ERR 
Excessive Transaction Error (XCS_XACT_ERR)
This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit 
when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will 
not be generated for Isochronous channels.
For non Scatter/Gather DMA mode, this bit is reserved.
Value Description
0x0 No Excessive Transaction Error
0x1 Excessive Transaction Error
RW 0x0
11 BNAIntr 
BNA (Buffer Not Available) Interrupt (BNAIntr)
This bit is valid only when Scatter/Gather DMA mode is enabled. 
The core generates this interrupt when the descriptor accessed 
is not ready for the Core to process. BNA will not be generated 
for Isochronous channels.
For non Scatter/Gather DMA mode, this bit is reserved.
Value Description
0x0 No BNA Interrupt
0x1 BNA Interrupt
RW 0x0
10 DataTglErr 
Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear
it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked 
in the core.
Value Description
0x0 No Data Toggle Error
0x1 Data Toggle Error
RW 0x0
9 FrmOvrun 
Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode, the interrupt due to this bit is masked 
in the core. This bit can be set only by the core and the application should write 1 to clear
it.
Value Description
0x0 No Frame Overrun
0x1 Frame Overrun
RW 0x0
8 BblErr 
Babble Error (BblErr)
In Scatter/Gather DMA mode, the interrupt due to this bit is masked 
in the core. This bit can be set only by the core and the application should write 1 to clear
it.
Value Description
0x0 No Babble Error
0x1 Babble Error
RW 0x0
7 XactErr 
Transaction Error (XactErr)
Indicates one of the following errors occurred on the USB.
 CRC check failure
 Timeout
 Bit stuff error
 False EOP
 In Scatter/Gather DMA mode, the interrupt due to this bit is masked 
 in the core.This bit can be set only by the core and the application should write 1 to clear
it.
Value Description
0x0 No Transaction Error
0x1 Transaction Error
RW 0x0
6 NYET 
NYET Response Received Interrupt (NYET)
In Scatter/Gather DMA mode, the interrupt due to this bit is masked 
in the core.This bit can be set only by the core and the application should write 1 to clear
it.
Value Description
0x0 No NYET Response Received Interrupt
0x1 NYET Response Received Interrupt
RW 0x0
5 ACK 
ACK Response Received/Transmitted Interrupt (ACK)
In Scatter/Gather DMA mode, the interrupt due to this bit is masked 
in the core.This bit can be set only by the core and the application should write 1 to clear
it.
Value Description
0x0 No ACK Response Received or Transmitted Interrupt
0x1 ACK Response Received or Transmitted Interrup
RW 0x0
4 NAK 
NAK Response Received Interrupt (NAK)
In Scatter/Gather DMA mode, the interrupt due to this bit is masked 
in the core.This bit can be set only by the core and the application should write 1 to clear
it.
Value Description
0x0 No NAK Response Received Interrupt
0x1 NAK Response Received Interrupt
RW 0x0
3 STALL 
STALL Response Received Interrupt (STALL)
In Scatter/Gather DMA mode, the interrupt due to this bit is masked 
in the core.This bit can be set only by the core and the application should write 1 to clear
it.
Value Description
0x0 No Stall Response Received Interrupt
0x1 Stall Response Received Interrupt
RW 0x0
2 AHBErr 
AHB Error (AHBErr)
This is generated only in Internal DMA mode when there is an
AHB error during AHB read/write. The application can read the
corresponding channel's DMA address register to get the error
address.
Value Description
0x0 No AHB error
0x1 AHB error during AHB read/write
RW 0x0
1 ChHltd 
Channel Halted (ChHltd)
In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.
in Scatter/gather DMA mode, this indicates that transfer completed due to any of the following
. EOL being set in descriptor
. AHB error
. Excessive transaction errors
. Babble
. Stall
Value Description
0x0 Channel not halted
0x1 Channel Halted
RW 0x0
0 XferCompl 
Transfer Completed (XferCompl)
Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.
For Scatter/Gather DMA mode, it indicates that current descriptor processing got
completed with IOC bit set in its descriptor.
In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without
any errors.
Value Description
0x0 Transfer in progress or No Active Transfer
0x1 Transfer completed normally without any errors
RW 0x0