reg_sideband13

         Sideband 13 Register

Module Instance	Base Address	Register Address
`iohmc_ctrl_inst_0_iohmc_ctrl_mmr_top_inst`	`0xF8010000`	`0xF80100E0`

Size: 32

Offset: 0xE0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`mr_cmd_opcode` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`mr_cmd_opcode` `RW 0x0`

reg_sideband13 Fields

Bit	Name	Description	Access	Reset
31:0	`mr_cmd_opcode`	iohmc_ctrl_mmr_top_inst.mr_cmd_opcode[31:0] Name:Mode Register Command Opcode Description:[31:27] reserved. Register Command Opcode Information to be used for Register Command LPDDR3 [26:20] Reserved [19:10] falling edge CA[9:0] [9:4] rising edge CA[9:4] [3:0] Reserved MRW: [19:12] is OP[7:0], [11:4] is MA[7:0] DDR4 [26:24] C2:C0 [23] ACT [22:21] BG1:BG0 [20] Reserved [19:18] BA1:BA0 [17] A17 [16] RAS# [15] CAS# [14] WE# [13:0] A13:A0 MRS: [22:21] is BG1:BG0, [19:18] is BA1:BA0, [13:0] is Opcode[13:0] DDR3 [26:21] Reserved [20:18] BA2:BA0 [17] A14 [16] RAS# [15] CAS# [14] WE# [13:0] A13:A0 MRS: [19:18] is BA1:BA0, [13:0] is Opcode[13:0]	`RW`	`0x0`

Bit

Name

Description

Access

Reset

31:0

mr_cmd_opcode

iohmc_ctrl_mmr_top_inst.mr_cmd_opcode[31:0]
Name:Mode Register Command Opcode
Description:[31:27] reserved.
Register Command Opcode
Information to be used for Register Command
LPDDR3
[26:20] Reserved
[19:10] falling edge CA[9:0]
[9:4] rising edge CA[9:4]
[3:0] Reserved
MRW: [19:12] is OP[7:0], [11:4] is MA[7:0]
DDR4
[26:24] C2:C0
[23] ACT
[22:21] BG1:BG0
[20] Reserved
[19:18] BA1:BA0
[17] A17
[16] RAS#
[15] CAS# 
[14] WE#
[13:0] A13:A0
MRS: [22:21] is BG1:BG0, [19:18] is BA1:BA0, [13:0] is Opcode[13:0]
DDR3
[26:21] Reserved
[20:18] BA2:BA0
[17] A14
[16] RAS#
[15] CAS# 
[14] WE# 
[13:0] A13:A0
MRS: [19:18] is BA1:BA0, [13:0] is Opcode[13:0]

RW

0x0