GINTSTS

Mode:Host and Device
Resume/Remote Wakeup Detected Interrupt (WkUpInt)
Wakeup Interrupt during Suspend(L2) or LPM(L1) state.
 During Suspend(L2):
- Device Mode - This interrupt is asserted only when Host Initiated
Resume is detected on USB.
- Host Mode - This interrupt is asserted only when Device Initiated
Remote Wakeup is detected on USB.
For more information, see 'Partial Power-Down and Clock Gating
Programming Model' in the Programming Guide.
 During LPM(L1):-
- Device Mode - This interrupt is asserted for either Host Initiated
Resume or Device Initiated Remote Wakeup on USB.
- Host Mode - This interrupt is asserted for either Host Initiated Resume
or Device Initiated Remote Wakeup on USB.
For more information, see 'LPM Entry and Exit Programming Model' in the Programming Guide.

Mode:Host and Device
Session Request/New Session Detected Interrupt (SessReqInt)
In Host mode, this interrupt is asserted when a session request is detected
from the device. In Host mode, this interrupt is asserted when a session
request is detected from the device.
In Device mode, this interrupt is asserted when the utmisrp_bvalid signal
goes high.
For more information on how to use this interrupt, see 'Partial Power-Down
and Clock Gating Programming Model' in the Programming Guide.

Mode:Host only
Disconnect Detected Interrupt (DisconnInt)
Asserted when a device disconnect is detected.

Mode:Host and Device
Connector ID Status Change (ConIDStsChng)
The core sets this bit when there is a change in connector ID
status.

Mode:Host only
Periodic TxFIFO Empty (PTxFEmp)
This interrupt is asserted when the Periodic Transmit FIFO is either half or
completely empty and there is space for at least one entry to be written in
the Periodic Request Queue. The half or completely empty status is
determined by the Periodic TxFIFO Empty Level bit in the Core AHB
Configuration register (GAHBCFG.PTxFEmpLvl).

Mode:Host only
Host Channels Interrupt (HChInt)
The core sets this bit to indicate that an interrupt is pending on
one of the channels of the core (in Host mode). The application
must read the Host All Channels Interrupt (HAINT) register to
determine the exact number of the channel on which the
interrupt occurred, and Then read the corresponding Host
Channel-n Interrupt (HCINTn) register to determine the exact
cause of the interrupt. The application must clear the
appropriate status bit in the HCINTn register to clear this bit.

Mode:Host only
Host Port Interrupt (PrtInt)
The core sets this bit to indicate a change in port status of one of
the DWC_otg core ports in Host mode. The application must
read the Host Port Control and Status (HPRT) register to
determine the exact event that caused this interrupt. The
application must clear the appropriate status bit in the Host Port
Control and Status register to clear this bit.

Mode: Device only
Reset detected Interrupt  (ResetDet)
In Device mode, this interrupt is asserted when a reset is detected on the USB in 
partial power-down mode when the device is in Suspend. 
In Host mode, this interrupt is not asserted.

Mode: Device only
Data Fetch Suspended (FetSusp)
This interrupt is valid only in DMA mode. This interrupt indicates
that the core has stopped fetching data For IN endpoints due to
the unavailability of TxFIFO space or Request Queue space.
This interrupt is used by the application For an endpoint
mismatch algorithm.
For example, after detecting an endpoint mismatch, the
application:
 Sets a Global non-periodic IN NAK handshake
 Disables In endpoints
 Flushes the FIFO
 Determines the token sequence from the IN Token Sequence
Learning Queue
 Re-enables the endpoints
 Clears the Global non-periodic IN NAK handshake
If the Global non-periodic IN NAK is cleared, the core has not yet
fetched data For the IN endpoint, and the IN token is received:
the core generates an 'IN token received when FIFO empty'
interrupt. The OTG Then sends the host a NAK response. To
avoid this scenario, the application can check the
GINTSTS.FetSusp interrupt, which ensures that the FIFO is full
before clearing a Global NAK handshake.
Alternatively, the application can mask the IN token received
when FIFO empty interrupt when clearing a Global IN NAK
handshake.

Incomplete Periodic Transfer (incomplP)
In Host mode, the core sets this interrupt bit when there are
incomplete periodic transactions still pending which are
scheduled For the current microframe.
Incomplete Isochronous OUT Transfer (incompISOOUT)
The Device mode, the core sets this interrupt to indicate that
there is at least one isochronous OUT endpoint on which the
transfer is not completed in the current microframe. This
interrupt is asserted along with the End of Periodic Frame
Interrupt (EOPF) bit in this register.

Mode: Device only
Incomplete Isochronous IN Transfer (incompISOIN)
The core sets this interrupt to indicate that there is at least one
isochronous IN endpoint on which the transfer is not completed
in the current microframe. This interrupt is asserted along with
the End of Periodic Frame Interrupt (EOPF) bit in this register.
Note: This interrupt is not asserted in Scatter/Gather DMA
mode.

Mode: Device only
OUT Endpoints Interrupt (OEPInt)
The core sets this bit to indicate that an interrupt is pending on
one of the OUT endpoints of the core (in Device mode). The
application must read the Device All Endpoints Interrupt (DAINT)
register to determine the exact number of the OUT endpoint on
which the interrupt occurred, and Then read the corresponding
Device OUT Endpoint-n Interrupt (DOEPINTn) register to
determine the exact cause of the interrupt. The application must
clear the appropriate status bit in the corresponding DOEPINTn
register to clear this bit.

Mode: Device only
IN Endpoints Interrupt (IEPInt)
The core sets this bit to indicate that an interrupt is pending on
one of the IN endpoints of the core (in Device mode). The
application must read the Device All Endpoints Interrupt (DAINT)
register to determine the exact number of the IN endpoint on
Device IN Endpoint-n Interrupt (DIEPINTn) register to determine
the exact cause of the interrupt. The application must clear the
appropriate status bit in the corresponding DIEPINTn register to
clear this bit.

Mode: Device only
Endpoint Mismatch Interrupt (EPMis)
Note: This interrupt is valid only in shared FIFO operation.
Indicates that an IN token has been received For a non-periodic
endpoint, but the data For another endpoint is present in the top
of the Non-periodic Transmit FIFO and the IN endpoint
mismatch count programmed by the application has expired.

Mode: Device only
End of Periodic Frame Interrupt (EOPF)
Indicates that the period specified in the Periodic Frame Interval
field of the Device Configuration register (DCFG.PerFrInt) has
been reached in the current microframe.

Mode: Device only
Isochronous OUT Packet Dropped Interrupt (ISOOutDrop)
The core sets this bit when it fails to write an isochronous OUT
packet into the RxFIFO because the RxFIFO does not have
enough space to accommodate a maximum packet size packet
for the isochronous OUT endpoint.

Mode: Device only
Enumeration Done (EnumDone)
The core sets this bit to indicate that speed enumeration is
complete. The application must read the Device Status (DSTS)
register to obtain the enumerated speed.

Mode: Device only
USB Reset (USBRst)
The core sets this bit to indicate that a reset is detected on the
USB.

Mode: Device only
USB Suspend (USBSusp)
The core sets this bit to indicate that a suspend was detected on
the USB. The core enters the Suspended state when there is no
activity on the linestate signal For an extended period of
time.

Mode: Device only
Early Suspend (ErlySusp)
The core sets this bit to indicate that an Idle state has been
detected on the USB For 3 ms.

Mode: Device only
Global OUT NAK Effective (GOUTNakEff)
Indicates that the Set Global OUT NAK bit in the Device Control
register (DCTL.SGOUTNak), Set by the application, has taken
effect in the core. This bit can be cleared by writing the Clear
Global OUT NAK bit in the Device Control register
(DCTL.CGOUTNak).

Mode: Device only
Global IN Non-periodic NAK Effective (GINNakEff)
Indicates that the Set Global Non-periodic IN NAK bit in the
Device Control register (DCTL.SGNPInNak) set by the
application, has taken effect in the core. That is, the core has
sampled the Global IN NAK bit Set by the application. This bit
can be cleared by clearing the Clear Global Non-periodic IN
NAK bit in the Device Control register (DCTL.CGNPInNak).
This interrupt does not necessarily mean that a NAK handshake
is sent out on the USB. The STALL bit takes precedence over
the NAK bit.

Mode: Host and Device 
Non-periodic TxFIFO Empty (NPTxFEmp)
This interrupt is asserted when the Non-periodic TxFIFO is
either half or completely empty, and there is space For at least
one Entry to be written to the Non-periodic Transmit Request
Queue. The half or completely empty status is determined by
the Non-periodic TxFIFO Empty Level bit in the Core AHB
Configuration register (GAHBCFG.NPTxFEmpLvl).

Mode: Host and Device
RxFIFO Non-Empty (RxFLvl)
Indicates that there is at least one packet pending to be read
from the RxFIFO.

Mode: Host and Device
Start of (micro)Frame (Sof)
In Host mode, the core sets this bit to indicate that an SOF (FS),
micro-SOF (HS), or Keep-Alive (LS) is transmitted on the USB.
The application must write a 1 to this bit to clear the interrupt.
In Device mode, in the core sets this bit to indicate that an SOF
token has been received on the USB. The application can read
the Device Status register to get the current (micro)Frame
number. This interrupt is seen only when the core is operating at
either HS or FS.

Note: This register may return 1'b1 if read immediately after power on
reset. If the register bit reads 1'b1 immediately after power on reset it does
not indicate that an SOF has been sent (in case of host mode) or SOF has
been received (in case of device mode). The read value of this interrupt is
valid only after a valid connection between host and device is established. If
the bit is set after power on reset the application can clear the bit.

Mode: Host and Device
OTG Interrupt (OTGInt)
The core sets this bit to indicate an OTG protocol event. The
application must read the OTG Interrupt Status (GOTGINT)
register to determine the exact event that caused this interrupt.
The application must clear the appropriate status bit in the
GOTGINT register to clear this bit.

Mode: Host and Device
Mode Mismatch Interrupt (ModeMis)
The core sets this bit when the application is trying to access:
 A Host mode register, when the core is operating in Device
mode
 A Device mode register, when the core is operating in Host
mode
The register access is completed on the AHB with an OKAY
response, but is ignored by the core internally and does not
affect the operation of the core.This bit can be set only by the core and the application should write 1 to clear
it

Mode: Host and Device
Current Mode of Operation (CurMod)
Indicates the current mode.
 1'b0: Device mode
 1'b1: Host mode