fpga2sdram0_axi64_I_main_QosGenerator_Priority 

         FPGA2SDRAM0 AXI-64 QoS Generator Priority Register
Module Instance Base Address Register Address
soc_ddr_scheduler_inst_0_fpga2sdram0_axi64_I_main_QosGenerator 0xF8022200 0xF8022208

Size: 32

Offset: 0x8

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MARK

RO 0x1

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

P1

RW 0x2

Reserved

P0

RW 0x0

fpga2sdram0_axi64_I_main_QosGenerator_Priority Fields

Bit Name Description Access Reset
31 MARK 
Backward compatibility marker when 0.
 RO 0x1
9:8 P1 
In Programmable or Bandwidth Limiter mode, the priority level for read transactions. In Bandwidth regulator mode, the priority level when the used throughput is below the threshold. In Bandwidth Regulator mode, P1 should have a value equal or greater than P0.
 RW 0x2
1:0 P0 
In Programmable or Bandwidth Limiter mode, the priority level for write transactions. In Bandwidth Regulator mode, the priority level when the used throughput is above the threshold. In Bandwidth Regulator mode, P0 should have a value equal or lower than P1.
 RW 0x0