transfer_spare_reg

         Default data transfer mode. (Ignored during Spare only mode)

Module Instance	Base Address	Register Address
`sdm_i_nand_config`	`0xFFA10000`	`0xFFA10010`

Size: 32

Offset: 0x10

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`															`flag` `RW 0x0`

transfer_spare_reg Fields

Bit	Name	Description	Access	Reset
0	`flag`	On all read or write commands through Map 01, if this bit is set, data in spare area of memory will be transfered to host along with main area of data. The main area will be transfered followed by spare area.[list][]1 - MAIN+SPARE []0 - MAIN[/list]	`RW`	`0x0`

Bit

Name

Description

Access

Reset

flag

On all read or write commands through Map 01, if this bit is set,
                                    data in spare area of memory will be transfered to host along with
                                    main area of data. The main area will be transfered followed by
                                    spare area.[list][*]1 - MAIN+SPARE [*]0 - MAIN[/list]

RW

0x0