ecc_enable

         Enable controller ECC check bit generation and correction

Module Instance	Base Address	Register Address
`sdm_i_nand_config`	`0xFFA10000`	`0xFFA100E0`

Size: 32

Offset: 0xE0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`															`flag` `RW 0x1`

ecc_enable Fields

Bit	Name	Description	Access	Reset
0	`flag`	Enables or disables controller ECC capabilities. When enabled, controller calculates ECC check-bits and writes them onto device on program operation. On page reads, check-bits are recomputed and errors reported, if any, after comparing with stored check-bits. When disabled, controller does not compute check-bits. [list][]1 - ECC Enabled []0 - ECC disabled[/list]	`RW`	`0x1`

Bit

Name

Description

Access

Reset

flag

Enables or disables controller ECC capabilities. When enabled, controller calculates
                            ECC check-bits and writes them onto device on program operation. On page reads,
                            check-bits are recomputed and errors reported, if any, after comparing with stored
                            check-bits. When disabled, controller does not compute check-bits.
                            [list][*]1 - ECC Enabled  [*]0 - ECC disabled[/list]

RW

0x1