probe_soc2fpga_main_Probe_Counters_3_PortSel
SoC2FPGA Probe Counter 3 Port Select Register
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_noc_ccu_ios_probe_soc2fpga_main_Probe | 0xFFD22C00 | 0xFFD22D70 |
Size: 32
Offset: 0x170
Access: RW
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
Reserved |
COUNTERS_3_PORTSEL RW 0x0 |
||||||||||||||
probe_soc2fpga_main_Probe_Counters_3_PortSel Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 0 | COUNTERS_3_PORTSEL |
Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time, with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection. |
RW | 0x0 |