SMMU_CB4_PRRR_MAIR0

         Primary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.

Note: For register and programming information, please refer to the Arm^® CoreLink™ MMU System Memory Management Unit Technical Reference Manual.

Module Instance	Base Address	Register Address
`i_aps_smmu_secure_registers`	`0xFA000000`	`0xFA024038`

Size: 32

Offset: 0x24038

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`NOS7` `RW 0x0`	`NOS6` `RW 0x0`	`NOS5` `RW 0x0`	`NOS4` `RW 0x0`	`NOS3` `RW 0x0`	`NOS2` `RW 0x0`	`NOS1` `RW 0x0`	`NOS0` `RW 0x0`	`Reserved`				`NS1` `RW 0x0`	`NS0` `RW 0x0`	`DS1` `RW 0x0`	`DS0` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`TR7` `RW 0x0`		`TR6` `RW 0x0`		`TR5` `RW 0x0`		`TR4` `RW 0x0`		`TR3` `RW 0x0`		`TR2` `RW 0x0`		`TR1` `RW 0x0`		`TR0` `RW 0x0`