INTMASK 

         Interrupt Mask Register
Module Instance Base Address Register Address
i_sdmmc_sdmmc_block 0xFF808000 0xFF808024

Size: 32

Offset: 0x24

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SDIO_INT_MASK_CARD15

RW 0x0

SDIO_INT_MASK_CARD14

RW 0x0

SDIO_INT_MASK_CARD13

RW 0x0

SDIO_INT_MASK_CARD12

RW 0x0

SDIO_INT_MASK_CARD11

RW 0x0

SDIO_INT_MASK_CARD10

RW 0x0

SDIO_INT_MASK_CARD9

RW 0x0

SDIO_INT_MASK_CARD8

RW 0x0

SDIO_INT_MASK_CARD7

RW 0x0

SDIO_INT_MASK_CARD6

RW 0x0

SDIO_INT_MASK_CARD5

RW 0x0

SDIO_INT_MASK_CARD4

RW 0x0

SDIO_INT_MASK_CARD3

RW 0x0

SDIO_INT_MASK_CARD2

RW 0x0

SDIO_INT_MASK_CARD1

RW 0x0

SDIO_INT_MASK_CARD0

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EBE_INT_MASK

RW 0x0

ACD_INT_MASK

RW 0x0

SBE_BCI_INT_MASK

RW 0x0

HLE_INT_MASK

RW 0x0

FRUN_INT_MASK

RW 0x0

HTO_INT_MASK

RW 0x0

DRTO_INT_MASK

RW 0x0

RTO_INT_MASK

RW 0x0

DCRC_INT_MASK

RW 0x0

RCRC_INT_MASK

RW 0x0

RXDR_INT_MASK

RW 0x0

TXDR_INT_MASK

RW 0x0

DTO_INT_MASK

RW 0x0

CMD_INT_MASK

RW 0x0

RE_INT_MASK

RW 0x0

CD_INT_MASK

RW 0x0

INTMASK Fields

Bit Name Description Access Reset
31 SDIO_INT_MASK_CARD15 
Mask SDIO interrupts
One bit for each card. Bit[31] corresponds to card[15], and bit[16] corresponds to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0 masks an interrupt, and 1 enables an interrupt.
In MMC-Ver3.3-only mode, these bits are always 0.
Value Description
0x0 Masks interrupt
0x1 Enables interrupt
RW 0x0
30 SDIO_INT_MASK_CARD14 
Mask SDIO interrupts
One bit for each card. Bit[31] corresponds to card[15], and bit[16] corresponds to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0 masks an interrupt, and 1 enables an interrupt.
In MMC-Ver3.3-only mode, these bits are always 0.
Value Description
0x0 Masks interrupt
0x1 Enables interrupt
RW 0x0
29 SDIO_INT_MASK_CARD13 
Mask SDIO interrupts
One bit for each card. Bit[31] corresponds to card[15], and bit[16] corresponds to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0 masks an interrupt, and 1 enables an interrupt.
In MMC-Ver3.3-only mode, these bits are always 0.
Value Description
0x0 Masks interrupt
0x1 Enables interrupt
RW 0x0
28 SDIO_INT_MASK_CARD12 
Mask SDIO interrupts
One bit for each card. Bit[31] corresponds to card[15], and bit[16] corresponds to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0 masks an interrupt, and 1 enables an interrupt.
In MMC-Ver3.3-only mode, these bits are always 0.
Value Description
0x0 Masks interrupt
0x1 Enables interrupt
RW 0x0
27 SDIO_INT_MASK_CARD11 
Mask SDIO interrupts
One bit for each card. Bit[31] corresponds to card[15], and bit[16] corresponds to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0 masks an interrupt, and 1 enables an interrupt.
In MMC-Ver3.3-only mode, these bits are always 0.
Value Description
0x0 Masks interrupt
0x1 Enables interrupt
RW 0x0
26 SDIO_INT_MASK_CARD10 
Mask SDIO interrupts
One bit for each card. Bit[31] corresponds to card[15], and bit[16] corresponds to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0 masks an interrupt, and 1 enables an interrupt.
In MMC-Ver3.3-only mode, these bits are always 0.
Value Description
0x0 Masks interrupt
0x1 Enables interrupt
RW 0x0
25 SDIO_INT_MASK_CARD9 
Mask SDIO interrupts
One bit for each card. Bit[31] corresponds to card[15], and bit[16] corresponds to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0 masks an interrupt, and 1 enables an interrupt.
In MMC-Ver3.3-only mode, these bits are always 0.
Value Description
0x0 Masks interrupt
0x1 Enables interrupt
RW 0x0
24 SDIO_INT_MASK_CARD8 
Mask SDIO interrupts
One bit for each card. Bit[31] corresponds to card[15], and bit[16] corresponds to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0 masks an interrupt, and 1 enables an interrupt.
In MMC-Ver3.3-only mode, these bits are always 0.
Value Description
0x0 Masks interrupt
0x1 Enables interrupt
RW 0x0
23 SDIO_INT_MASK_CARD7 
Mask SDIO interrupts
One bit for each card. Bit[31] corresponds to card[15], and bit[16] corresponds to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0 masks an interrupt, and 1 enables an interrupt.
In MMC-Ver3.3-only mode, these bits are always 0.
Value Description
0x0 Masks interrupt
0x1 Enables interrupt
RW 0x0
22 SDIO_INT_MASK_CARD6 
Mask SDIO interrupts
One bit for each card. Bit[31] corresponds to card[15], and bit[16] corresponds to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0 masks an interrupt, and 1 enables an interrupt.
In MMC-Ver3.3-only mode, these bits are always 0.
Value Description
0x0 Masks interrupt
0x1 Enables interrupt
RW 0x0
21 SDIO_INT_MASK_CARD5 
Mask SDIO interrupts
One bit for each card. Bit[31] corresponds to card[15], and bit[16] corresponds to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0 masks an interrupt, and 1 enables an interrupt.
In MMC-Ver3.3-only mode, these bits are always 0.
Value Description
0x0 Masks interrupt
0x1 Enables interrupt
RW 0x0
20 SDIO_INT_MASK_CARD4 
Mask SDIO interrupts
One bit for each card. Bit[31] corresponds to card[15], and bit[16] corresponds to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0 masks an interrupt, and 1 enables an interrupt.
In MMC-Ver3.3-only mode, these bits are always 0.
Value Description
0x0 Masks interrupt
0x1 Enables interrupt
RW 0x0
19 SDIO_INT_MASK_CARD3 
Mask SDIO interrupts
One bit for each card. Bit[31] corresponds to card[15], and bit[16] corresponds to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0 masks an interrupt, and 1 enables an interrupt.
In MMC-Ver3.3-only mode, these bits are always 0.
Value Description
0x0 Masks interrupt
0x1 Enables interrupt
RW 0x0
18 SDIO_INT_MASK_CARD2 
Mask SDIO interrupts
One bit for each card. Bit[31] corresponds to card[15], and bit[16] corresponds to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0 masks an interrupt, and 1 enables an interrupt.
In MMC-Ver3.3-only mode, these bits are always 0.
Value Description
0x0 Masks interrupt
0x1 Enables interrupt
RW 0x0
17 SDIO_INT_MASK_CARD1 
Mask SDIO interrupts
One bit for each card. Bit[31] corresponds to card[15], and bit[16] corresponds to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0 masks an interrupt, and 1 enables an interrupt.
In MMC-Ver3.3-only mode, these bits are always 0.
Value Description
0x0 Masks interrupt
0x1 Enables interrupt
RW 0x0
16 SDIO_INT_MASK_CARD0 
Mask SDIO interrupts
One bit for each card. Bit[31] corresponds to card[15], and bit[16] corresponds to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0 masks an interrupt, and 1 enables an interrupt.
In MMC-Ver3.3-only mode, these bits are always 0.
Value Description
0x0 Masks interrupt
0x1 Enables interrupt
RW 0x0
15 EBE_INT_MASK 
End-bit error (read)/Write no CRC (EBE) interrupt enable. 
                                                 Value of 0 masks interrupt; value of 1 enables interrupt.
Value Description
0x0 Masks interrupt
0x1 Enables interrupt
RW 0x0
14 ACD_INT_MASK 
Auto command done (ACD) interrupt enable. 
                                                 Value of 0 masks interrupt; value of 1 enables interrupt.
Value Description
0x0 Masks interrupt
0x1 Enables interrupt
RW 0x0
13 SBE_BCI_INT_MASK 
Start Bit Error(SBE)/Busy Complete Interrupt (BCI) interrupt enable. 
                                                 Value of 0 masks interrupt; value of 1 enables interrupt.
Value Description
0x0 Masks interrupt
0x1 Enables interrupt
RW 0x0
12 HLE_INT_MASK 
Hardware locked write error (HLE) interrupt enable. 
                                                 Value of 0 masks interrupt; value of 1 enables interrupt.
Value Description
0x0 Masks interrupt
0x1 Enables interrupt
RW 0x0
11 FRUN_INT_MASK 
FIFO underrun/overrun error (FRUN) interrupt enable. 
                                                 Value of 0 masks interrupt; value of 1 enables interrupt.
Value Description
0x0 Masks interrupt
0x1 Enables interrupt
RW 0x0
10 HTO_INT_MASK 
Data starvation-by-host timeout (HTO) /Volt_switch_int interrupt enable. 
                                                 Value of 0 masks interrupt; value of 1 enables interrupt.
Value Description
0x0 Masks interrupt
0x1 Enables interrupt
RW 0x0
9 DRTO_INT_MASK 
Data read timeout (DRTO) interrupt enable. 
                                                 Value of 0 masks interrupt; value of 1 enables interrupt.
Value Description
0x0 Masks interrupt
0x1 Enables interrupt
RW 0x0
8 RTO_INT_MASK 
Response timeout (RTO) interrupt enable. 
                                                 Value of 0 masks interrupt; value of 1 enables interrupt.
Value Description
0x0 Masks interrupt
0x1 Enables interrupt
RW 0x0
7 DCRC_INT_MASK 
Data CRC error (DCRC) interrupt enable. 
                                                 Value of 0 masks interrupt; value of 1 enables interrupt.
Value Description
0x0 Masks interrupt
0x1 Enables interrupt
RW 0x0
6 RCRC_INT_MASK 
Response CRC error (RCRC) interrupt enable. 
                                                 Value of 0 masks interrupt; value of 1 enables interrupt.
Value Description
0x0 Masks interrupt
0x1 Enables interrupt
RW 0x0
5 RXDR_INT_MASK 
Receive FIFO data request (RXDR) interrupt enable. 
                                                 Value of 0 masks interrupt; value of 1 enables interrupt.
Value Description
0x0 Masks interrupt
0x1 Enables interrupt
RW 0x0
4 TXDR_INT_MASK 
Transmit FIFO data request (TXDR) interrupt enable. 
                                                 Value of 0 masks interrupt; value of 1 enables interrupt.
Value Description
0x0 Masks interrupt
0x1 Enables interrupt
RW 0x0
3 DTO_INT_MASK 
Data transfer over (DTO) interrupt enable. 
                                                 Value of 0 masks interrupt; value of 1 enables interrupt.
Value Description
0x0 Masks interrupt
0x1 Enables interrupt
RW 0x0
2 CMD_INT_MASK 
Command done (CD) interrupt enable
                                                 Value of 0 masks interrupt; value of 1 enables interrupt.
Value Description
0x0 Masks interrupt
0x1 Enables interrupt
RW 0x0
1 RE_INT_MASK 
Response error (RE) interrupt enable. 
                                                 Value of 0 masks interrupt; value of 1 enables interrupt.
Value Description
0x0 Masks interrupt
0x1 Enables interrupt
RW 0x0
0 CD_INT_MASK 
Card detect (CD) interrupt enable. 
                                                 Value of 0 masks interrupt; value of 1 enables interrupt.
Value Description
0x0 Masks interrupt
0x1 Enables interrupt
RW 0x0