gmacgrp_lpi_timers_control
Register 13 (LPI Timers Control Register)
The LPI Timers Control register controls the timeout values in the LPI states. It specifies the time for which the MAC transmits the LPI pattern and also the time for which the MAC waits before resuming the normal transmission. This register is present only when you select the Energy Efficient Ethernet feature during core configuration.
Module Instance | Base Address | Register Address |
---|---|---|
i_emac_emac0 | 0xFF800000 | 0xFF800034 |
i_emac_emac1 | 0xFF802000 | 0xFF802034 |
i_emac_emac2 | 0xFF804000 | 0xFF804034 |
Size: 32
Offset: 0x34
Access: RW
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
reserved_31_26 RO 0x0 |
lst RW 0x3E8 |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
twt RW 0x0 |
gmacgrp_lpi_timers_control Fields
Bit | Name | Description | Access | Reset |
---|---|---|---|---|
31:26 | reserved_31_26 |
Reserved |
RO | 0x0 |
25:16 | lst |
LPI LS Timer This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count. The default value of the LPI LS Timer is 1000 (1 sec) as defined in the IEEE standard. |
RW | 0x3E8 |
15:0 | twt |
LPI TW Timer This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission. The TLPIEX status bit is set after the expiry of this timer. |
RW | 0x0 |