reg_dramtiming0

         DRAM Timing 0 Register

Module Instance	Base Address	Register Address
`iohmc_ctrl_inst_0_iohmc_ctrl_mmr_top_inst`	`0xF8010000`	`0xF8010050`

Size: 32

Offset: 0x50

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`													`cfg_mem_clk_disable_entry_cycles` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`cfg_mem_clk_disable_entry_cycles` `RO 0x0`			`cfg_power_saving_exit_cycles` `RO 0x0`						`cfg_tcl` `RO 0x0`

reg_dramtiming0 Fields

Bit	Name	Description	Access	Reset
18:13	`cfg_mem_clk_disable_entry_cycles`	iohmc_ctrl_mmr_top_inst.cfg_mem_clk_disable_entry_cycles[5:0] Name:Clock Disable Delay Cycles Description:Set to a the number of clocks after the execution of an self-refresh to stop the clock. This register is generally set based on PHY design latency and should generally not be changed.	`RO`	`0x0`
12:7	`cfg_power_saving_exit_cycles`	iohmc_ctrl_mmr_top_inst.cfg_power_saving_exit_cycles[5:0] Name:Minimum Low Power State Cycles Description:The minimum number of cycles to stay in a low power state. This applies to both power down and self-refresh and should be set to the greater of tPD and tCKESR.	`RO`	`0x0`
6:0	`cfg_tcl`	iohmc_ctrl_mmr_top_inst.cfg_tcl[6:0] Name:CAS Read Latency Description:Memory read latency.	`RO`	`0x0`

Bit

Name

Description

Access

Reset

18:13

cfg_mem_clk_disable_entry_cycles

iohmc_ctrl_mmr_top_inst.cfg_mem_clk_disable_entry_cycles[5:0]
Name:Clock Disable Delay Cycles
Description:Set to a the number of clocks after the execution of an self-refresh to stop the clock. This register is generally set based on PHY design latency and should generally not be changed.

RO

0x0

12:7

cfg_power_saving_exit_cycles

iohmc_ctrl_mmr_top_inst.cfg_power_saving_exit_cycles[5:0]
Name:Minimum Low Power State Cycles
Description:The minimum number of cycles to stay in a low power state. This applies to both power down and self-refresh and should be set to the greater of tPD and tCKESR.

RO

0x0

6:0

cfg_tcl

iohmc_ctrl_mmr_top_inst.cfg_tcl[6:0]
Name:CAS Read Latency
Description:Memory read latency.

RO

0x0