IC_TX_ABRT_SOURCE

         Name: I2C Transmit Abort Source Register
Size: 32 bits
Address Offset: 0x80
Read/Write Access: Read
This register has 32 bits that indicate the source
of the TX_ABRT bit. Except for Bit 9, this register is
cleared whenever the IC_CLR_TX_ABRT register or the
IC_CLR_INTR register is read. To clear Bit 9, the source
of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must
be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared
(IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]).
Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this
bit can be cleared in the same manner as other bits in this
register. If the source of the ABRT_SBYTE_NORSTRT is not fixed
before attempting to clear this bit, Bit 9 clears for one cycle
and is then re-asserted.
      
Module Instance Base Address Register Address
sdm_i2c_0_DW_apb_i2c_addr_block0 0xFF8D0100 0xFF8D0180
sdm_i2c_1_DW_apb_i2c_addr_block1 0xFF8D0200 0xFF8D0280

Size: 32

Offset: 0x80

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

TX_FLUSH_CNT

RO 0x0

RSVD_IC_TX_ABRT_SOURCE

RO 0x0

RSVD_ABRT_DEVICE_WRITE

RO 0x0

RSVD_ABRT_SDA_STUCK_AT_LOW

RO 0x0

ABRT_USER_ABRT

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ABRT_SLVRD_INTX

RO 0x0

ABRT_SLV_ARBLOST

RO 0x0

ABRT_SLVFLUSH_TXFIFO

RO 0x0

ARB_LOST

RO 0x0

ABRT_MASTER_DIS

RO 0x0

ABRT_10B_RD_NORSTRT

RO 0x0

ABRT_SBYTE_NORSTRT

RO 0x0

ABRT_HS_NORSTRT

RO 0x0

ABRT_SBYTE_ACKDET

RO 0x0

ABRT_HS_ACKDET

RO 0x0

ABRT_GCALL_READ

RO 0x0

ABRT_GCALL_NOACK

RO 0x0

ABRT_TXDATA_NOACK

RO 0x0

ABRT_10ADDR2_NOACK

RO 0x0

ABRT_10ADDR1_NOACK

RO 0x0

ABRT_7B_ADDR_NOACK

RO 0x0

IC_TX_ABRT_SOURCE Fields

Bit Name Description Access Reset
31:23 TX_FLUSH_CNT
This field indicates the 
number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. 
It is cleared whenever I2C is disabled.
Reset value: 0x0
Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter
RO 0x0
22:21 RSVD_IC_TX_ABRT_SOURCE
Reserved bits - Read Only
RO 0x0
20:18 RSVD_ABRT_DEVICE_WRITE
Reserved bits - Read Only
RO 0x0
17 RSVD_ABRT_SDA_STUCK_AT_LOW


                     
RO 0x0
16 ABRT_USER_ABRT
This is a master-mode-only bit. Master has 
detected the transfer abort (IC_ENABLE[1])
Reset value: 0x0
Role of DW_apb_i2c: Master-Transmitter
Value Description
0x0 Transfer abort detected by master- scenario not present
0x1 Transfer abort detected by master
RO 0x0
15 ABRT_SLVRD_INTX
1: When the processor side responds to
a slave mode request for data to be
transmitted to a remote master and user
writes a 1 in CMD (bit 8) of
IC_DATA_CMD register.
Dependencies: This field is not applicable  when IC_ULTRA_FAST_MODE=1
Reset value: 0x0
Role of DW_apb_i2c: Slave-Transmitter
Value Description
0x0 Slave trying to transmit to remote master in read mode- scenario not present
0x1 Slave trying to transmit to remote master in read mode
RO 0x0
14 ABRT_SLV_ARBLOST
1: Slave lost the bus while transmitting
data to a remote master.
IC_TX_ABRT_SOURCE[12] is set at
the same time.
Note: Even though the slave never
'owns' the bus, something could go
wrong on the bus. This is a fail safe
check. For instance, during a data
transmission at the low-to-high
transition of SCL, if what is on the data
bus is not what is supposed to be
transmitted, then DW_apb_i2c no
longer own the bus.
Dependencies: This field is not applicable  when IC_ULTRA_FAST_MODE=1
Reset value: 0x0
Role of DW_apb_i2c: Slave-Transmitter
Value Description
0x0 Slave lost arbitration to remote master- scenario not present
0x1 Slave lost arbitration to remote master
RO 0x0
13 ABRT_SLVFLUSH_TXFIFO
1: Slave has received a read command
and some data exists in the TX FIFO so
the slave issues a TX_ABRT interrupt to
flush old data in TX FIFO.
Dependencies: This field is not applicable  when IC_ULTRA_FAST_MODE=1
Reset value: 0x0
Role of DW_apb_i2c: Slave-Transmitter
Value Description
0x0 Slave flushes existing data in TX-FIFO upon getting read command- scenario not present
0x1 Slave flushes existing data in TX-FIFO upon getting read command
RO 0x0
12 ARB_LOST
1: Master has lost arbitration, or if
IC_TX_ABRT_SOURCE[14] is also
set, then the slave transmitter has lost
arbitration.
Dependencies: This field is not applicable  when IC_ULTRA_FAST_MODE=1
Reset value: 0x0
Role of DW_apb_i2c: Master-Transmitter
                    or Slave-Transmitter
Value Description
0x0 Master or Slave-Transmitter lost arbitration- scenario not present
0x1 Master or Slave-Transmitter lost arbitration
RO 0x0
11 ABRT_MASTER_DIS
1: User tries to initiate a Master
operation with the Master mode disabled.
Reset value: 0x0
Role of DW_apb_i2c: Master-Transmitter
                    or Master-Receiver
Value Description
0x0 User initiating master operation when MASTER disabled- scenario not present
0x1 User intitating master operation when MASTER disabled
RO 0x0
10 ABRT_10B_RD_NORSTRT
1: The restart is disabled
(IC_RESTART_EN bit (IC_CON[5]) =0)
and the master sends a read
command in 10-bit addressing mode.
Dependencies: This field is not applicable  when IC_ULTRA_FAST_MODE=1
Reset value: 0x0
Role of DW_apb_i2c: Master-Receiver
Value Description
0x0 Master not trying to read in 10Bit addressing mode when RESTART disabled
0x1 Master trying to read in 10Bit addressing mode when RESTART disabled
RO 0x0
9 ABRT_SBYTE_NORSTRT
To clear Bit 9, the source of the
ABRT_SBYTE_NORSTRT must be fixed first;
restart must be enabled (IC_CON[5]=1),
the SPECIAL bit must be cleared (IC_TAR[11]),
or the GC_OR_START bit must be cleared
(IC_TAR[10]). Once the source of the
ABRT_SBYTE_NORSTRT is fixed,
then this bit can be cleared in the same
manner as other bits in this register. If
the source of the ABRT_SBYTE_NORSTRT is not fixed
before attempting to clear this bit, bit 9
clears for one cycle and then gets reasserted.
1: The restart is disabled (IC_RESTART_EN bit
   (IC_CON[5]) =0) and the user is trying to
   send a START Byte.
Reset value: 0x0
Role of DW_apb_i2c: Master
Value Description
0x0 User trying to send START byte when RESTART disabled- scenario not present
0x1 User trying to send START byte when RESTART disabled
RO 0x0
8 ABRT_HS_NORSTRT
1: The restart is disabled
(IC_RESTART_EN bit (IC_CON[5]) =0)
and the user is trying to use the
master to transfer data in High Speed
mode.
Dependencies: This field is not applicable  when IC_ULTRA_FAST_MODE=1
Reset value: 0x0
Role of DW_apb_i2c: Master-Transmitter
                    or Master-Receiver
Value Description
0x0 User trying to switch Master to HS mode when RESTART disabled- scenario not present
0x1 User trying to switch Master to HS mode when RESTART disabled
RO 0x0
7 ABRT_SBYTE_ACKDET
1: Master has sent a START Byte and
the START Byte was acknowledged (wrong behavior).
Dependencies: This field is not applicable  when IC_ULTRA_FAST_MODE=1
Reset value: 0x0
Role of DW_apb_i2c: Master
Value Description
0x0 ACK detected for START byte- scenario not present
0x1 ACK detected for START byte
RO 0x0
6 ABRT_HS_ACKDET
1: Master is in High Speed mode and
the High Speed Master code was
acknowledged (wrong behavior).
Dependencies: This field is not applicable  when IC_ULTRA_FAST_MODE=1
Reset value: 0x0
Role of DW_apb_i2c: Master
Value Description
0x0 HS Master code ACKed in HS Mode- scenario not present
0x1 HS Master code ACKed in HS Mode
RO 0x0
5 ABRT_GCALL_READ
1: DW_apb_i2c in master mode sent a
General Call but the user programmed
the byte following the General Call to
be a read from the bus
(IC_DATA_CMD[9] is set to 1).
Dependencies: This field is not applicable  when IC_ULTRA_FAST_MODE=1
Reset value: 0x0
Role of DW_apb_i2c: Master-Transmitter
Value Description
0x0 GCALL is followed by read from bus-scenario not present
0x1 GCALL is followed by read from bus
RO 0x0
4 ABRT_GCALL_NOACK
1: DW_apb_i2c in master mode sent a
General Call and no slave on the bus
acknowledged the General Call.
Dependencies: This field is not applicable  when IC_ULTRA_FAST_MODE=1
Reset value: 0x0
Role of DW_apb_i2c: Master-Transmitter
Value Description
0x0 GCALL not ACKed by any slave-scenario not present
0x1 GCALL not ACKed by any slave
RO 0x0
3 ABRT_TXDATA_NOACK
1: This is a master-mode only bit.
Master has received an
acknowledgement for the address, but
when it sent data byte(s) following the
address, it did not receive an
acknowledge from the remote slave(s).
Dependencies: This field is not applicable  when IC_ULTRA_FAST_MODE=1
Reset value: 0x0
Role of DW_apb_i2c: Master-Transmitter
Value Description
0x0 Transmitted data non-ACKed by addressed slave-scenario not present
0x1 Transmitted data not ACKed by addressed slave
RO 0x0
2 ABRT_10ADDR2_NOACK
1: Master is in 10-bit address mode and
the second address byte of the 10-bit
address was not acknowledged by any slave.
Dependencies: This field is not applicable  when IC_ULTRA_FAST_MODE=1
Reset value: 0x0
Role of DW_apb_i2c: Master-Transmitter
                    or Master-Receiver
Value Description
0x0 This abort is not generated
0x1 Byte 2 of 10Bit Address not ACKed by any slave
RO 0x0
1 ABRT_10ADDR1_NOACK
1: Master is in 10-bit address mode and
the first 10-bit address byte was not
acknowledged by any slave.
Dependencies: This field is not applicable  when IC_ULTRA_FAST_MODE=1
Reset value: 0x0
Role of DW_apb_i2c: Master-Transmitter
                    or Master-Receiver
Value Description
0x0 This abort is not generated
0x1 Byte 1 of 10Bit Address not ACKed by any slave
RO 0x0
0 ABRT_7B_ADDR_NOACK
1: Master is in 7-bit addressing mode
and the address sent was not
acknowledged by any slave.
Dependencies: This field is not applicable  when IC_ULTRA_FAST_MODE=1
Reset value: 0x0
Role of DW_apb_i2c: Master-Transmitter
                    or Master-Receiver
Value Description
0x0 This abort is not generated
0x1 This abort is generated because of NOACK for 7-bit address
RO 0x0