gmacgrp_pps0_interval

         The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0]).

Module Instance	Base Address	Register Address
`i_emac_emac0`	`0xFF800000`	`0xFF800760`
`i_emac_emac1`	`0xFF802000`	`0xFF802760`
`i_emac_emac2`	`0xFF804000`	`0xFF804760`

Size: 32

Offset: 0x760

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`ppsint` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`ppsint` `RW 0x0`

gmacgrp_pps0_interval Fields

Bit	Name	Description	Access	Reset
31:0	`ppsint`	These bits store the interval between the rising edges of PPS0 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS0 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 -1) in this register.	`RW`	`0x0`

Bit

Name

Description

Access

Reset

31:0

ppsint

These bits store the interval between the rising edges of PPS0 signal output in terms of units of sub-second increment value. 
You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS0 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 -1) in this register.

RW

0x0