SMMU_NSGFSR

         Gives the fault status for each of the following possible faults.
      
Note: For register and programming information, please refer to the Arm® CoreLink™ MMU System Memory Management Unit Technical Reference Manual.
Module Instance Base Address Register Address
i_aps_smmu_secure_registers 0xFA000000 0xFA000448

Size: 32

Offset: 0x448

Access: WO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MULTI

WO 0x0

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

UUT

WO 0x0

Reserved

EF

WO 0x0

CAF

WO 0x0

UCIF

WO 0x0

UCBF

WO 0x0

SMCF

WO 0x0

USF

WO 0x0

ICF

WO 0x0