GIC_VCPUifVM Address Map

Memory map for the GIC virtual CPU interface. Contains all registers with the GICV prefix. Note: This provides access to the virtual CPU interface for the current CPU. It is expected that software will use the translation tables to make this block accessible to the virtual machine in the address space normall used for the (physical) CPU interface. For details of these registers, please refer to the Arm^® CoreLink™ GIC-400 Generic Interrupt Controller Technical Reference Manual.

Module Instance	Base Address	End Address
`i_gic_wrapper_VCPUifVM`	`0xFFFC6000`	`0xFFFC7FFF`

Register	Offset	Width	Access	Reset Value	Description
`GICV_CTLR`	`0x0`	`32`	`RW`	`0x00000000`	Virtual Machine Control Register
`GICV_PMR`	`0x4`	`32`	`RW`	`0x00000000`	VM Priority Mask Register
`GICV_BPR`	`0x8`	`32`	`RW`	`0x00000002`	VM Binary Point Register
`GICV_IAR`	`0xC`	`32`	`RO`	`0x000003FF`	VM Interrupt Acknowledge Register
`GICV_EOIR`	`0x10`	`32`	`WO`	`0x0`	VM End of Interrupt Register
`GICV_RPR`	`0x14`	`32`	`RO`	`0x000000FF`	VM Running Priority Register
`GICV_HPPIR`	`0x18`	`32`	`RO`	`0x000003FF`	VM Highest Priority Pending Interrupt Register
`GICV_ABPR`	`0x1C`	`32`	`RW`	`0x00000003`	VM Aliased Binary Point Register
`GICV_AIAR`	`0x20`	`32`	`RO`	`0x000003FF`	VM Aliased Interrupt Acknowledge Register
`GICV_AEOIR`	`0x24`	`32`	`WO`	`0x0`	VM Aliased End of Interrupt Register
`GICV_AHPPIR`	`0x28`	`32`	`RO`	`0x000003FF`	VM Aliased Highest Priority Pending Interrupt Register
`GICV_APR0`	`0xD0`	`32`	`RW`	`0x00000000`	VM Active Priority Register
`GICV_IIDR`	`0xFC`	`32`	`RO`	`0x0202143B`	VM CPU Interface Identification Register
`GICV_DIR`	`0x1000`	`32`	`WO`	`0x0`	VM Deactivate Interrupt Register