BAUDR 

         Baud Rate Select.
This register is valid only when the DW_apb_ssi is configured as a master
device. When the DW_apb_ssi is configured as a serial slave, writing to
this location has no effect; reading from this location returns 0. The
register derives the frequency of the serial clock that regulates the data
transfer. The 16-bit field in this register defines the ssi_clk divider
value. It is impossible to write to this register when the DW_apb_ssi is
enabled. The DW_apb_ssi is enabled and disabled by writing to the SSIENR
register.
Module Instance Base Address Register Address
i_spim_0_ssi_address_block 0xFFDA4000 0xFFDA4014
i_spim_1_ssi_address_block 0xFFDA5000 0xFFDA5014

Size: 32

Offset: 0x14

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD_BAUDR

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SCKDV

RW 0x0

BAUDR Fields

Bit Name Description Access Reset
31:16 RSVD_BAUDR 
Reserved bits - Read Only
 RO 0x0
15:0 SCKDV 
SSI Clock Divider.
The LSB for this field is always set to 0 and is unaffected by a write
operation, which ensures an even value is held in this register. If the
value is 0, the serial output clock (sclk_out) is disabled. The frequency
of the sclk_out is derived from the following equation: 



        Fsclk_out = Fssi_clk/SCKDV



where SCKDV is any even value between 2 and 65534. For example:
for Fssi_clk = 3.6864MHz and SCKDV =2
Fsclk_out = 3.6864/2 = 1.8432MHz
 RW 0x0