ERRINTENS 

         Error Interrupt set
Module Instance Base Address Register Address
soc_hmc_adp_csr_inst_0_ocp_slv_block 0xF8011000 0xF8011114

Size: 32

Offset: 0x114

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

SEQ2CORE_INTRS

0x0

HMI_INTRS

0x0

DERRINTS

0x0

SERRINTS

0x0

ERRINTENS Fields

Bit Name Description Access Reset
3 SEQ2CORE_INTRS 
This bit is used to set the seq2core interrupt.
1'b0: writing of zero has no effect
1'b1: writing one, SEQ2CORE_INTREN bit to 1
This is performing a bitwise writing, not implemented as a FF.
Value Description
0 STAY
1 SET
RW 0x0
2 HMI_INTRS 
This bit is used to set the general purposes HMI interrupt error.
1'b0: writing of zero has no effect
1'b1: writing one, HMI_INTREN bit to 1. 
This is performing a bitwise writing, not implemented as a FF.
Value Description
0 STAY
1 SET
RW 0x0
1 DERRINTS 
This bit is used to set the double-bit error interrupt bit.
Reads reflect DERRINTEN.
1'b0: writing of zero has no effect
1'b1: writing one, DERRINTEN bit to 1. 
This is performing a bitwise writing, not implemented as a FF.
Value Description
0 STAY
1 SET
RW 0x0
0 SERRINTS 
This bit is used to set the single-bit error interrupt bit.
Reads reflect SERRINTEN.
1'b0: writing of zero has no effect
1'b1: writing one, this bit will set SERRINTEN bit to 1. 
This is performing a bitwise writing, not implemented as a FF.
Value Description
0 STAY
1 SET
RW 0x0