GUSBCFG

Mode:Host and device
Corrupt Tx packet
This bit is for debug purposes only. Never Set this bit to 1.The application should always write 1'b0 to this bit.

Mode:Host and device
Force Device Mode (ForceDevMode)
Writing a 1 to this bit forces the core to device mode irrespective
of utmiotg_iddig input pin.
 1'b0 : Normal Mode.
 1'b1 : Force Device Mode.
After setting the force bit, the application must wait at least 25 ms before
the change to take effect. When the simulation is in scale down mode,
waiting for 500 micro sec is sufficient.

Mode:Host and device
Force Host Mode (ForceHstMode)
Writing a 1 to this bit forces the core to host mode irrespective of
utmiotg_iddig input pin.
 1'b0 : Normal Mode.
 1'b1 : Force Host Mode.
After setting the force bit, the application must wait at least 25 ms before
the change to take effect. When the simulation is in scale down mode,
waiting for 500 micro sec is sufficient.

Mode: Device only
Tx End Delay (TxEndDelay)
Writing 1'b1 to this bit enables the core to follow the TxEndDelay timings as per UTMI+ specification  1.05 section 4.1.5 for opmode signal during remote wakeup.  
 1'b0 : Normal Mode.
 1'b1 : Tx End delay.

IC_USB-Capable (IC_USBCap)
The application uses this bit to control the DWC_otg core's IC_USB
capabilities.
 1'b0: IC_USB PHY Interface is not selected.
 1'b1: IC_USB PHY Interface is selected.
This bit is writable only if IC_USB is selected

Mode:Host only
ULPI Interface Protect Disable
Controls circuitry built into the PHY For protecting the ULPI
interface when the link tri-states STP and data.
Any pull-ups or pull-downs employed by this feature can be
disabled. Please refer to the ULPI Specification For more detail.
 1'b0: Enables the interface protect circuit
 1'b1: Disables the interface protect circuit

Mode:Host only
Indicator Pass Through
Controls wether the Complement Output is qualified with the
Internal Vbus Valid comparator before being used
in the Vbus State in the RX CMD. Please refer to the ULPI Spec
for more detail.
 1'b0: Complement Output signal is qualified with the Internal
VbusValid comparator.
 1'b1: Complement Output signal is not qualified with the
Internal VbusValid comparator.

Mode:Host only
Indicator Complement
Controls the PHY to invert the ExternalVbusIndicator input
signal, generating the Complement
Output. Please refer to the ULPI Spec For more detail
 1'b0: PHY does not invert ExternalVbusIndicator signal
 1'b1: PHY does invert ExternalVbusIndicator signal

Mode:Device only
TermSel DLine Pulsing Selection (TermSelDLPulse)
This bit selects utmi_termselect to drive data line pulse during
SRP.
 1'b0: Data line pulsing using utmi_txvalid (Default).
 1'b1: Data line pulsing using utmi_termsel.

Mode:Host only
ULPI External VBUS Indicator (ULPIExtVbusIndicator)
This bit indicates to the ULPI PHY to use an external VBUS overcurrent
indicator.
 1'b0: PHY uses internal VBUS valid comparator.
 1'b1: PHY uses external VBUS valid comparator.

Mode:Host only
ULPI External VBUS Drive (ULPIExtVbusDrv)
This bit selects between internal or external supply to drive 5V
on VBUS, in ULPI PHY.
 1'b0: PHY drives VBUS using internal charge pump (Default).
 1'b1: PHY drives VBUS using external supply.

Mode:Host and Device
ULPI Clock SuspendM (ULPIClkSusM)
This bit sets the ClockSuspendM bit in the Interface Control
register on the ULPI PHY. This bit applies only in serial or carkit
modes.
 1'b0: PHY powers down internal clock during suspend.
 1'b1: PHY does not power down internal clock.

Mode:Host and Device
ULPI Auto Resume (ULPIAutoRes)
This bit sets the AutoResume bit in the Interface Control register
on the ULPI PHY.
 1'b0: PHY does not use AutoResume feature.
 1'b1: PHY uses AutoResume feature.

RESERVED

Mode: Device only
USB Turnaround Time (USBTrdTim)
Sets the turnaround time in PHY clocks.
Specifies the response time For a MAC request to the Packet
FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM).
This must be programmed to
 4'h5: When the MAC interface is 16-bit UTMI+ .
 4'h9: When the MAC interface is 8-bit UTMI+ .
Note: The values above are calculated For the minimum AHB
frequency of 30 MHz. USB turnaround time is critical For
certification where long cables and 5-Hubs are used, so If you
need the AHB to run at less than 30 MHz, and If USB turnaround
time is not critical, these bits can be programmed to a larger
value.

Mode:Host and Device
HNP-Capable (HNPCap)
The application uses this bit to control the DWC_otg core's HNP
capabilities.
 1'b0: HNP capability is not enabled.
 1'b1: HNP capability is enabled.

Mode:Host and Device
SRP-Capable (SRPCap)
The application uses this bit to control the DWC_otg core SRP
capabilities. If the core operates as a non-SRP-capable 
B-device, it cannot request the connected A-device (host) to
activate VBUS and start a session.
 1'b0: SRP capability is not enabled.
 1'b1: SRP capability is enabled.

Mode:Host and Device
ULPI DDR Select (DDRSel)
The application uses this bit to select a Single Data Rate (SDR)
or Double Data Rate (DDR) or ULPI interface.
 1'b0: Single Data Rate ULPI Interface, with 8-bit-wide data
bus
 1'b1: Double Data Rate ULPI Interface, with 4-bit-wide data
bus

Mode:Host and Device
USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial
Transceiver Select (PHYSel)
The application uses this bit to select either a high-speed UTMI+
or ULPI PHY, or a full-speed transceiver.
 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY
 1'b1: USB 1.1 full-speed serial transceiver
If a USB 1.1 Full-Speed Serial Transceiver interface was not
selected in, this bit is always 0, with Write Only access.
If a high-speed PHY interface was not selected in,
this bit is always 1, with Write Only access.
If both interface types were selected (parameters have non-zero values), 
the application uses this bit to select which interface is active, 
and access is Read and Write.

Mode:Host and Device
Full-Speed Serial Interface Select (FSIntf)
The application uses this bit to select either a unidirectional or
bidirectional USB 1.1 full-speed serial transceiver interface.
 1'b0: 6-pin unidirectional full-speed serial interface
 1'b1: 3-pin bidirectional full-speed serial interface
If a USB 1.1 Full-Speed Serial Transceiver interface was not
selected, this bit is always 0, with Write
Only access. If a USB 1.1 FS interface was selected, Then the
application can Set this bit to select between the 3- and 6-pin
interfaces, and access is Read and Write.

Mode:Host and Device
ULPI or UTMI+ Select (ULPI_UTMI_Sel)
The application uses this bit to select either a UTMI+ interface or
ULPI Interface.
 1'b0: UTMI+ Interface
 1'b1: ULPI Interface
This bit is writable only If UTMI+ and ULPI was specified For
High-Speed PHY Interface(s).

Mode:Host and Device
PHY Interface (PHYIf)
The application uses this bit to configure the core to support a
UTMI+ PHY with an 8- or 16-bit interface. When a ULPI PHY is
chosen, this must be Set to 8-bit mode.
 1'b0: 8 bits
 1'b1: 16 bits
This bit is writable only If UTMI+ and ULPI were selected

Mode:Host and Device
HS/FS Timeout Calibration (TOutCal)
The number of PHY clocks that the application programs in this
field is added to the high-speed/full-speed interpacket timeout
duration in the core to account For any additional delays
introduced by the PHY. This can be required, because the delay
introduced by the PHY in generating the linestate condition can
vary from one PHY to another.
The USB standard timeout value For high-speed operation is 736
to 816 (inclusive) bit times. The USB standard timeout value For
full-speed operation is 16 to 18 (inclusive) bit times. The
application must program this field based on the speed of
enumeration. The number of bit times added per PHY clock are:
High-speed operation:
 One 30-MHz PHY clock = 16 bit times
 One 60-MHz PHY clock = 8 bit times
Full-speed operation:
 One 30-MHz PHY clock = 0.4 bit times
 One 60-MHz PHY clock = 0.2 bit times
 One 48-MHz PHY clock = 0.25 bit times