FPGA_bridge_soc2fpga_2.5G Address Map
2.5 GB of FPGA slaves address space. This space is located in the FPGA core and
accessed from the HPS through the HPS-FPGA AXI bridge. The L3 and MPU address regions provide windows of 4 GB
into the FPGA slaves address space. The lower 1.5 GB of this space is mapped to two separate addresses. The lower
1.5 GB is accessible from 0x8000_0000 to 0xDFFF_FFFF and from 0x20_0000_0000 to 0x20_5FFF_FFFF in the HPS system memory map. This block represents the rest of the 4 GB space starting at 0x20_6000_0000.
| Module Instance | Base Address | End Address |
|---|---|---|
| i_fpga_bridge_soc2fpga_2.5G | 0x2060000000 | 0x20FFFFFFFF |