SMMU_S2CR53

         Specifies an initial context for processing a transaction, where the transaction matches the Stream mapping group that this register belongs to.

Note: For register and programming information, please refer to the Arm^® CoreLink™ MMU System Memory Management Unit Technical Reference Manual.

Module Instance	Base Address	Register Address
`i_aps_smmu_secure_registers`	`0xFA000000`	`0xFA000CD4`

Size: 32

Offset: 0xCD4

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`		`TRANSIENTCFG` `RW 0x0`		`INSTCFG_1` `RW 0x0`	`INSTCFG_0_FB` `RW 0x0`	`PRIVCFG_BSU` `RW 0x0`		`WACFG` `RW 0x0`		`RACFG` `RW 0x0`		`NSCFG` `RW 0x0`		`TYPE` `RW 0x2`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`MEM_ATTR` `RW 0x0`				`MTCFG` `RW 0x0`	`Reserved`	`SHCFG` `RW 0x0`		`CBNDX_VMID` `RW 0x0`