dmagrp_interrupt_enable

          Register 7 (Interrupt Enable Register) 

The Interrupt Enable register enables the interrupts reported by Register 5 (Status Register). Setting a bit to 1'b1 enables a corresponding interrupt. After a hardware or software reset, all interrupts are disabled.
      
Module Instance Base Address Register Address
i_emac_emac0 0xFF800000 0xFF80101C
i_emac_emac1 0xFF802000 0xFF80301C
i_emac_emac2 0xFF804000 0xFF80501C

Size: 32

Offset: 0x101C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved_31_17

RO 0x0

nie

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

aie

RW 0x0

ere

RW 0x0

fbe

RW 0x0

reserved_12_11

RO 0x0

ete

RW 0x0

rwe

RW 0x0

rse

RW 0x0

rue

RW 0x0

rie

RW 0x0

une

RW 0x0

ove

RW 0x0

tje

RW 0x0

tue

RW 0x0

tse

RW 0x0

tie

RW 0x0

dmagrp_interrupt_enable Fields

Bit Name Description Access Reset
31:17 reserved_31_17
Reserved
RO 0x0
16 nie
Normal Interrupt Summary Enable

When this bit is set, normal interrupt summary is enabled. When this bit is reset, normal interrupt summary is disabled. This bit enables the following interrupts in Register 5 (Status Register):
 * Register 5[0]: Transmit Interrupt
 * Register 5[2]: Transmit Buffer Unavailable
 * Register 5[6]: Receive Interrupt
 * Register 5[14]: Early Receive Interrupt
Value Description
0x0 DISABLED
0x1 ENABLED
RW 0x0
15 aie
Abnormal Interrupt Summary Enable

When this bit is set, abnormal interrupt summary is enabled. When this bit is reset, the abnormal interrupt summary is disabled. This bit enables the following interrupts in Register 5 (Status Register):
 * Register 5[1]: Transmit Process Stopped
 * Register 5[3]: Transmit Jabber Timeout
 * Register 5[4]: Receive Overflow
 * Register 5[5]: Transmit Underflow
 * Register 5[7]: Receive Buffer Unavailable
 * Register 5[8]: Receive Process Stopped
 * Register 5[9]: Receive Watchdog Timeout
 * Register 5[10]: Early Transmit Interrupt
 * Register 5[13]: Fatal Bus Error
Value Description
0x0 DISABLED
0x1 ENABLED
RW 0x0
14 ere
Early Receive Interrupt Enable

When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Early Receive Interrupt is enabled. When this bit is reset, the Early Receive Interrupt is disabled.
Value Description
0x0 DISABLED
0x1 ENABLED
RW 0x0
13 fbe
Fatal Bus Error Enable

When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Fatal Bus Error Interrupt is enabled. When this bit is reset, the Fatal Bus Error Enable Interrupt is disabled.
Value Description
0x0 DISABLED
0x1 ENABLED
RW 0x0
12:11 reserved_12_11
Reserved
RO 0x0
10 ete
Early Transmit Interrupt Enable

When this bit is set with an Abnormal Interrupt Summary Enable (Bit 15), the Early Transmit Interrupt is enabled. When this bit is reset, the Early Transmit Interrupt is disabled.
Value Description
0x0 DISABLED
0x1 ENABLED
RW 0x0
9 rwe
Receive Watchdog Timeout Enable

When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, the Receive Watchdog Timeout Interrupt is disabled.
Value Description
0x0 DISABLED
0x1 ENABLED
RW 0x0
8 rse
Receive Stopped Enable

When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Stopped Interrupt is enabled. When this bit is reset, the Receive Stopped Interrupt is disabled.
Value Description
0x0 DISABLED
0x1 ENABLED
RW 0x0
7 rue
Receive Buffer Unavailable Enable

When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled.
RW 0x0
6 rie
Receive Interrupt Enable

When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Receive Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled.
Value Description
0x0 DISABLED
0x1 ENABLED
RW 0x0
5 une
Underflow Interrupt Enable

When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Underflow Interrupt is enabled. When this bit is reset, the Underflow Interrupt is disabled.
Value Description
0x0 DISABLED
0x1 ENABLED
RW 0x0
4 ove
Overflow Interrupt Enable

When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Overflow Interrupt is enabled. When this bit is reset, the Overflow Interrupt is disabled.
Value Description
0x0 DISABLED
0x1 ENABLED
RW 0x0
3 tje
Transmit Jabber Timeout Enable

When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, the Transmit Jabber Timeout Interrupt is disabled.
Value Description
0x0 DISABLED
0x1 ENABLED
RW 0x0
2 tue
Transmit Buffer Unavailable Enable

When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled.
Value Description
0x0 DISABLED
0x1 ENABLED
RW 0x0
1 tse
Transmit Stopped Enable

When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmission Stopped Interrupt is enabled. When this bit is reset, the Transmission Stopped Interrupt is disabled.
Value Description
0x0 DISABLED
0x1 ENABLED
RW 0x0
0 tie
Transmit Interrupt Enable

When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Interrupt is enabled. When this bit is reset, the Transmit Interrupt is disabled.
Value Description
0x0 DISABLED
0x1 ENABLED
RW 0x0