por_reset_count

         The number of cycles the controller waits after POR to issue the first RESET command
                            to the device.

Module Instance	Base Address	Register Address
`sdm_i_nand_config`	`0xFFA10000`	`0xFFA102A0`

Size: 32

Offset: 0x2A0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`value` `RW 0x13B`

por_reset_count Fields

Bit	Name	Description	Access	Reset
15:0	`value`	The controller waits for this number of cycles before issuing the first RESET command to the device. The number in this register is multiplied internally by 16 in the controller to form the final reset wait count.	`RW`	`0x13B`

Bit

Name

Description

Access

Reset

15:0

value

The controller waits for this number of cycles before issuing the first 
                                  RESET command to the device. The number in this register is multiplied
                                  internally by 16 in the controller to form the final reset wait count.

RW

0x13B