cs_obs_at_main_ErrorLogger_0_StallEn

         CoreSight Observer Main Error Logger 0 Stall Enable Register
      
Module Instance Base Address Register Address
i_noc_ccu_ios_cs_obs_at_main_ErrorLogger_0 0xFFD22080 0xFFD220B8

Size: 32

Offset: 0x38

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

STALLEN

RW 0x0

cs_obs_at_main_ErrorLogger_0_StallEn Fields

Bit Name Description Access Reset
0 STALLEN
Set to 1 to enable stall mode behavior.
RW 0x0