GHWCFG3 

         User HW Config3 Register
Module Instance Base Address Register Address
i_usbotg_0_DWC_otg_intreg 0xFFB00000 0xFFB0004C
i_usbotg_1_DWC_otg_intreg 0xFFB40000 0xFFB4004C

Size: 32

Offset: 0x4C

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DfifoDepth

RO 0x1F80

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LPMMode

RO 0x0

BCSupport

RO 0x0

HSICMode

RO 0x0

ADPSupport

RO 0x0

RstType

RO 0x0

OptFeature

RO 0x0

VndctlSupt

RO 0x1

I2CIntSel

RO 0x0

OtgEn

RO 0x1

PktSizeWidth

RO 0x6

XferSizeWidth

RO 0x8

GHWCFG3 Fields

Bit Name Description Access Reset
31:16 DfifoDepth 
DFIFO Depth (DfifoDepth - EP_LOC_CNT)
This value is in terms of 32-bit words.
 Minimum value is 32
 Maximum value is 32,768
RO 0x1F80
15 LPMMode 
LPM mode specified for Mode of Operation.
Value Description
0x0 LPM disabled
0x1 LPM enabled
RO 0x0
14 BCSupport 
This bit indicates the HS OTG controller support for Battery Charger.
 0 - No Battery Charger Support
 1 - Battery Charger support present.
Value Description
0x0 No Battery Charger Support
0x1 Battery Charger Support present
RO 0x0
13 HSICMode 
HSIC mode specified for Mode of Operation
Value Range: 0 - 1
 1: HSIC-capable with shared UTMI PHY interface
 0: Non-HSIC-capable
Value Description
0x0 No HSIC capability
0x1 HSIC-capable with shared UTMI PHY interface
RO 0x0
12 ADPSupport 
This bit indicates whether ADP logic is present within or external to the HS OTG
controller
 0: No ADP logic present with DWC_otg controller
 1: ADP logic is present along with DWC_otg controller.
Value Description
0x0 ADP logic is not present along with DWC_otg controller
0x1 ADP logic is present along with DWC_otg controller
RO 0x0
11 RstType 
Reset Style For Clocked always Blocks in RTL (RstType)
 1'b0: Asynchronous reset is used in the core
 1'b1: Synchronous reset is used in the core
Value Description
0x0 Asynchronous reset is used in the core
0x1 Synchronous reset is used in the core
RO 0x0
10 OptFeature 
Optional Features Removed (OptFeature)
Indicates whether the User ID register, GPIO interface ports,
and SOF toggle and counter ports were removed for gate count
optimization by enabling Remove Optional Features.
 1'b0: No
 1'b1: Yes
Value Description
0x0 Optional features were not Removed
0x1 Optional Features have been Removed
RO 0x0
9 VndctlSupt 
Vendor Control Interface Support (VndctlSupt)
 1'b0: Vendor Control Interface is not available on the core.
 1'b1: Vendor Control Interface is available.
Value Description
0x0 Vendor Control Interface is not available.
0x1 Vendor Control Interface is available.
RO 0x1
8 I2CIntSel 
I2C Selection (I2CIntSel)
 1'b0: I2C Interface is not available on the core.
 1'b1: I2C Interface is available on the core.
Value Description
0x0 I2C Interface is not available
0x1 I2C Interface is available
RO 0x0
7 OtgEn 
OTG Function Enabled (OtgEn)
The application uses this bit to indicate the DWC_otg core's
OTG capabilities.
 1'b0: Not OTG capable
 1'b1: OTG Capable
Value Description
0x0 Not OTG Capable
0x1 OTG Capable
RO 0x1
6:4 PktSizeWidth 
Width of Packet Size Counters (PktSizeWidth)
 3'b000: 4 bits
 3'b001: 5 bits
 3'b010: 6 bits
 3'b011: 7 bits
 3'b100: 8 bits
 3'b101: 9 bits
 3'b110: 10 bits
 Others: Reserved
Value Description
0x0 Width of Packet Size Counter 4
0x1 Width of Packet Size Counter 5
0x2 Width of Packet Size Counter 6
0x3 Width of Packet Size Counter 7
0x4 Width of Packet Size Counter 8
0x5 Width of Packet Size Counter 9
0x6 Width of Packet Size Counter 10
RO 0x6
3:0 XferSizeWidth 
Width of Transfer Size Counters (XferSizeWidth)
 4'b0000: 11 bits
 4'b0001: 12 bits
...
 4'b1000: 19 bits
 Others: Reserved
Value Description
0x0 Width of Transfer Size Counter 11 bits
0x1 Width of Transfer Size Counter 12 bits
0x2 Width of Transfer Size Counter 13 bits
0x3 Width of Transfer Size Counter 14 bits
0x4 Width of Transfer Size Counter 15 bits
0x5 Width of Transfer Size Counter 16 bits
0x6 Width of Transfer Size Counter 17 bits
0x7 Width of Transfer Size Counter 18 bits
0x8 Width of Transfer Size Counter 19 bits
RO 0x8