reg_sideband7

         Sideband 7 Register
      
Module Instance Base Address Register Address
iohmc_ctrl_inst_0_iohmc_ctrl_mmr_top_inst 0xF8010000 0xF80100C8

Size: 32

Offset: 0xC8

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mmr_refresh_ack

RO 0x0

reg_sideband7 Fields

Bit Name Description Access Reset
0 mmr_refresh_ack
iohmc_ctrl_mmr_top_inst.mmr_refresh_ack
Name:Refresh Acknowlege (non-3DS)
Description: Acknowledge signal for refresh request. When asserted indicates refresh is in progress. Asserts when refresh request is sent out to PHY until tRFC/t_param_arf_to_valid is fulfilled
RO 0x0