ECC_DECSTAT 

         Diagnostic decoder status
Module Instance Base Address Register Address
soc_hmc_adp_csr_inst_0_ocp_slv_block 0xF8011000 0xF8011154

Size: 32

Offset: 0x154

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

DEC3DERRFLG

0x0

DEC2DERRFLG

0x0

DEC1DERRFLG

0x0

DEC0DERRFLG

0x0

DEC3ADDRFLG

0x0

DEC2ADDRFLG

0x0

DEC1ADDRFLG

0x0

DEC0ADDRFLG

0x0

DEC3SERRFLG

0x0

DEC2SERRFLG

0x0

DEC1SERRFLG

0x0

DEC0SERRFLG

0x0

ECC_DECSTAT Fields

Bit Name Description Access Reset
11 DEC3DERRFLG 
indicates decoder for data [255:192] has detected DBE.
1'b0: No error has been captured with this flag. 
1'b1: Decoder 0 detected a double-bit error. This flag will be set by the hardware and it will be cleared by the writing 1. This flag will be set till SW clears. Additional errors will not change the state of this bit. Error flag is set on the first beat of erred data.
This won't be reset by the ecc_en bit.
 RW 0x0
10 DEC2DERRFLG 
indicates decoder for data [191:128] has detected DBE.
1'b0: No error has been captured with this flag. 
1'b1: Decoder 0 detected a double-bit error. This flag will be set by the hardware and it will be cleared by the writing 1. This flag will be set till SW clears. Additional errors will not change the state of this bit.Error flag is set on the first beat of erred data.
This won't be reset by the ecc_en bit.
 RW 0x0
9 DEC1DERRFLG 
indicates decoder for data [127:64] has detected DBE.
1'b0: No error has been captured with this flag. 
1'b1: Decoder 0 detected a double-bit error. This flag will be set by the hardware and it will be cleared by the writing 1. This flag will be set till SW clears. Additional errors will not change the state of this bit.Error flag is set on the first beat of erred data.
This won't be reset by the ecc_en bit.
 RW 0x0
8 DEC0DERRFLG 
indicates decoder for data [63:0] has detected DBE.
1'b0: No error has been captured with this flag. 
1'b1: Decoder 0 detected a double-bit error. This flag will be set by the hardware and it will be cleared by the writing 1. This flag will be set till SW clears. Additional errors will not change the state of this bit. Error flag is set on the first beat of erred data.
This won't be reset by the ecc_en bit.
 RW 0x0
7 DEC3ADDRFLG 
indicates decoder for data [255:192] has detected address error.
1'b0: No error has been captured with this flag. 
1'b1: Decoder 0 detected an address mismatch error. This flag will be set by the hardware and it will be cleared by the writing 1. This flag will be set till SW clears.Additional errors will not change the state of this bit.Error flag is set on the first beat of erred data.
This won't be reset by the ecc_en bit.
 RW 0x0
6 DEC2ADDRFLG 
indicates decoder for data [191:128] has detected address error.
1'b0: No error has been captured with this flag. 
1'b1: Decoder 0 detected an address mismatch error. This flag will be set by the hardware and it will be cleared by the writing 1. This flag will be set till SW clears.Additional errors will not change the state of this bit.Error flag is set on the first beat of erred data.
This won't be reset by the ecc_en bit.
 RW 0x0
5 DEC1ADDRFLG 
indicates decoder for data [127:64] has detected address error.
1'b0: No error has been captured with this flag. 
1'b1: Decoder 0 detected an address mismatch error. This flag will be set by the hardware and it will be cleared by the writing 1. This flag will be set till SW clears.Additional errors will not change the state of this bit.Error flag is set on the first beat of erred data.
This won't be reset by the ecc_en bit.
 RW 0x0
4 DEC0ADDRFLG 
indicates decoder for data [63:0] has detected address error.
1'b0: No error has been captured with this flag. 
1'b1: Decoder 0 detected an address mismatch error. This flag will be set by the hardware and it will be cleared by the writing 1. This flag will be set till SW clears.Additional errors will not change the state of this bit.Error flag is set on the first beat of erred data.
This won't be reset by the ecc_en bit.
 RW 0x0
3 DEC3SERRFLG 
indicates decoder for data [255:192] has detected SBE.
1'b0: No error has been captured with this flag. 
1'b1: Decoder 0 detected a single bit error. This flag will be set by the hardware and it will be cleared by the writing 1. This flag will be set till SW clears. Additional errors will not change the state of this bit.Error flag is set on the first beat of erred data.
This won't be reset by the ecc_en bit.
 RW 0x0
2 DEC2SERRFLG 
indicates decoder for data [191:128] has detected SBE.
1'b0: No error has been captured with this flag. 
1'b1: Decoder 0 detected a single bit error. This flag will be set by the hardware and it will be cleared by the writing 1. This flag will be set till SW clears. Additional errors will not change the state of this bit.Error flag is set on the first beat of erred data.
This won't be reset by the ecc_en bit.
 RW 0x0
1 DEC1SERRFLG 
indicates decoder for data [127:64] has detected SBE.
1'b0: No error has been captured with this flag. 
1'b1: Decoder 0 detected a single bit error. This flag will be set by the hardware and it will be cleared by the writing 1. This flag will be set till SW clears. Additional errors will not change the state of this bit. Error flag is set on the first beat of erred data.
This won't be reset by the ecc_en bit.
 RW 0x0
0 DEC0SERRFLG 
indicates decoder for data [63:0] has detected SBE.
1'b0: No error has been captured with this flag. 
1'b1: Decoder 0 detected a single bit error. This flag will be set by the hardware and it will be cleared by the writing 1. This flag will be set till SW clears. Additional errors will not change the state of this bit. Error flag is set on the first beat of erred data.
This won't be reset by the ecc_en bit.
 RW 0x0