srbr_sthr_3

         This is multi-function register. It is shadow register for Receive Buffer Register and Transmit Holding Register.

Module Instance	Base Address	Register Address
`i_uart_0_uart_address_block`	`0xFFC02000`	`0xFFC0203C`
`i_uart_1_uart_address_block`	`0xFFC02100`	`0xFFC0213C`

Size: 32

Offset: 0x3C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`rsvd_srbr_sthr_3_31to8` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`rsvd_srbr_sthr_3_31to8` `RO 0x0`								`srbr_sthr_3` `RO 0x0`

srbr_sthr_3 Fields

Bit	Name	Description	Access	Reset
31:8	`rsvd_srbr_sthr_3_31to8`	Reserved bits [31:8] - Read Only	`RO`	`0x0`
7:0	`srbr_sthr_3`	See srbr_sthr_0 description	`RO`	`0x0`