delay

          This register is used to introduce relative delays into the generation of the master output signals. All timings are defined in cycles of the SPI REFERENCE CLOCK/ext_clk, defined in this table as SPI master ref clock. 
      
Module Instance Base Address Register Address
sdm_qspi_qspiregs 0xFF8D2000 0xFF8D200C

Size: 32

Offset: 0xC

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

nss

RW 0x0

btwn

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

after

RW 0x0

init

RW 0x0

delay Fields

Bit Name Description Access Reset
31:24 nss
 Delay in master reference clocks for the length that the master mode chip select outputs are de-asserted between transactions. The minimum delay is always SCLK period to ensure the chip select is never re-asserted within an SCLK period. 
RW 0x0
23:16 btwn
 Delay in master reference clocks between one chip select being de-activated and the activation of another. This is used to ensure a quiet period between the selection of two different slaves and requires the transmit FIFO to be empty. 
RW 0x0
15:8 after
 Delay in master reference clocks between last bit of current transaction and deasserting the device chip select (n_ss_out). By default, the chip select will be deasserted on the cycle following the completion of the current transaction. 
RW 0x0
7:0 init
 Delay in master reference clocks between setting n_ss_out low and first bit transfer.  
RW 0x0