reg_ctrlcfg0

         Control Configuration 0 Register

Module Instance	Base Address	Register Address
`iohmc_ctrl_inst_0_iohmc_ctrl_mmr_top_inst`	`0xF8010000`	`0xF8010028`

Size: 32

Offset: 0x28

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`			`cfg_dbc2_burst_length` `RO 0x0`					`cfg_dbc1_burst_length` `RO 0x0`					`cfg_dbc0_burst_length` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`cfg_dbc0_burst_length` `RO 0x0`		`cfg_ctrl_burst_length` `RO 0x0`					`cfg_ac_pos` `RO 0x0`		`cfg_dimm_type` `RO 0x0`			`cfg_mem_type` `RO 0x0`

reg_ctrlcfg0 Fields

Bit	Name	Description	Access	Reset
28:24	`cfg_dbc2_burst_length`	iohmc_ctrl_mmr_top_inst.cfg_dbc2_burst_length[4:0] Name:DBC2 – DRAM Memory Burst Length Description:Configures burst length for DBC2. Legal values are valid for JEDEC allowed DRAM values for the DRAM selected in cfg_type. For DDR3, DDR4 and LPDDR3, this should be programmed with 8 (binary “01000”).	`RO`	`0x0`
23:19	`cfg_dbc1_burst_length`	iohmc_ctrl_mmr_top_inst.cfg_dbc1_burst_length[4:0] Name:DBC1 – DRAM Memory Burst Length Description:Configures burst length for DBC1. Legal values are valid for JEDEC allowed DRAM values for the DRAM selected in cfg_type. For DDR3, DDR4 and LPDDR3, this should be programmed with 8 (binary “01000”).	`RO`	`0x0`
18:14	`cfg_dbc0_burst_length`	iohmc_ctrl_mmr_top_inst.cfg_dbc0_burst_length[4:0] Name:DBC0 – DRAM Memory Burst Length Description:Configures burst length for DBC0. Legal values are valid for JEDEC allowed DRAM values for the DRAM selected in cfg_type. For DDR3, DDR4 and LPDDR3, this should be programmed with 8 (binary “01000”).	`RO`	`0x0`
13:9	`cfg_ctrl_burst_length`	iohmc_ctrl_mmr_top_inst.cfg_ctrl_burst_length[4:0] Name:Control – DRAM Memory Burst Length Description:Configures burst length for control path. Legal values are valid for JEDEC allowed DRAM values for the DRAM selected in cfg_type. For DDR3, DDR4 and LPDDR3, this should be programmed with 8 (binary “01000”).	`RO`	`0x0`
8:7	`cfg_ac_pos`	iohmc_ctrl_mmr_top_inst.cfg_ac_pos[1:0] Name:A/C pin position Description:Specify C/A (command/address) pin position. 2’b00 – three lanes are used as C/A pins, Lane0, 1 and 2; 2’b01 - three lanes are used as C/A pins, Lane1, 2 and 3; 2’b10 - All four lanes are used as C/A pins.	`RO`	`0x0`
6:4	`cfg_dimm_type`	iohmc_ctrl_mmr_top_inst.cfg_dimm_type[2:0] Name:DIMM Type Description:Selects dimm type. Program this field with one of the following binary values, “3’b000” for Component, “3’b001” for UDIMM, “3’b010” for RDIMM, “3’b011” for LRDIMM and “3’b100” for SODIMM.	`RO`	`0x0`
3:0	`cfg_mem_type`	iohmc_ctrl_mmr_top_inst.cfg_mem_type[3:0] Name:DRAM Memory Type Description:Selects memory type. Program this field with one of the following binary values, “0000” for DDR3 SDRAM, “0001” for DDR4 SDRAM and “0010” for LPDDR3 SDRAM.	`RO`	`0x0`