far

         FIFO Access Register
      
Module Instance Base Address Register Address
i_uart_0_uart_address_block 0xFFC02000 0xFFC02070
i_uart_1_uart_address_block 0xFFC02100 0xFFC02170

Size: 32

Offset: 0x70

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

rsvd_far_31to1

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

rsvd_far_31to1

RO 0x0

srbr_sthr

RW 0x0

far Fields

Bit Name Description Access Reset
31:1 rsvd_far_31to1
Reserved bits [31:1] - Read Only
RO 0x0
0 srbr_sthr
Writes will have no effect when FIFO_ACCESS == No, always readable.  This register
is use to enable a FIFO access mode for testing, so that the receive FIFO can be
written by the master and the transmit FIFO can be read by the master when FIFO's
are implemented and enabled. When FIFO's are not implemented or not enabled it
allows the RBR to be written by the master and the THR to be read by the master.
0 = FIFO access mode disabled
1 = FIFO access mode enabled
Note, that when the FIFO access mode is enabled/disabled, the control portion of
the receive FIFO and transmit FIFO is reset and the FIFO's are treated as empty.
Value Description
0 FIFO access mode disabled
1 FIFO access mode enabled
RW 0x0