reg_sideband12

         Sideband 12 Register

Module Instance	Base Address	Register Address
`iohmc_ctrl_inst_0_iohmc_ctrl_mmr_top_inst`	`0xF8010000`	`0xF80100DC`

Size: 32

Offset: 0xDC

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`									`mr_cmd_rank` `RW 0x0`				`mr_cmd_type` `RW 0x0`

reg_sideband12 Fields

Bit	Name	Description	Access	Reset
6:3	`mr_cmd_rank`	iohmc_ctrl_mmr_top_inst.mr_cmd_rank[3:0] Name:Mode Register Command Rank Description:Indicates the rank targeted by Register Command 0001 - CS0 0010 - CS1 0011 - CS0 and CS1 ... 1111 - All CS Mode Register Set - any combination of CS	`RW`	`0x0`
2:0	`mr_cmd_type`	iohmc_ctrl_mmr_top_inst.mr_cmd_type[2:0] Name:Mode Register Command Type Description:Set to indicate the type of Register Command 000 - Mode Register Set (DDR3, DDR4 and LPDDR3) Others - Reserved.	`RW`	`0x0`

Bit

Name

Description

Access

Reset

6:3

mr_cmd_rank

iohmc_ctrl_mmr_top_inst.mr_cmd_rank[3:0]
Name:Mode Register Command Rank
Description:Indicates the rank targeted by Register Command
0001 - CS0
0010 - CS1
0011 - CS0 and CS1
...
1111 - All CS
Mode Register Set - any combination of CS

RW

0x0

2:0

mr_cmd_type

iohmc_ctrl_mmr_top_inst.mr_cmd_type[2:0]
Name:Mode Register Command Type
Description:Set to indicate the type of Register Command
000 - Mode Register Set (DDR3, DDR4 and LPDDR3)
Others - Reserved.

RW

0x0