stet

         Shadow TX Empty Trigger
      
Module Instance Base Address Register Address
i_uart_0_uart_address_block 0xFFC02000 0xFFC020A0
i_uart_1_uart_address_block 0xFFC02100 0xFFC021A0

Size: 32

Offset: 0xA0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

rsvd_stet_31to2

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

rsvd_stet_31to2

RO 0x0

stet

RW 0x0

stet Fields

Bit Name Description Access Reset
31:2 rsvd_stet_31to2
Reserved bits [31:2] - Read Only
RO 0x0
1:0 stet
Shadow TX Empty Trigger.
This is a shadow register for the TX empty trigger bits (FCR[5:4]). This can be used
to remove the burden of having to store the previously written value to the FCR in
memory and having to mask this value so that only the TX empty trigger bit gets updated.
Writes will have no effect when THRE_MODE_USER == Disabled. This is used to select the
empty threshold level at which the THRE Interrupts will be generated when the mode is
active. These threshold levels are also described in. The following trigger levels are
supported:
00 = FIFO empty
01 = 2 characters in the FIFO
10 = FIFO � full
11 = FIFO � full
Value Description
0 FIFO empty
1 Two characters in FIFO
2 FIFO quarter full
3 FIFO half full
RW 0x0