ier_dlh

         This is a multi-function register. This register enables/disables receive and transmit interrupts and also controls the most-significant 8-bits of the baud rate divisor.
Divisor Latch High Register:
This register is accessed when the DLAB bit [7] of the LCR Register is set to 1.Bits[7:0] contain the high order 8-bits of the baud rate divisor.The output baud rate is equal to the serial clock l4_sp_clk frequency divided by sixteen times the value of the baud rate divisor, as follows:
baud rate = (serial clock freq) / (16 * divisor):
Note that with the Divisor Latch Registers (DLLand DLH) set to zero, the baud clock is disabled and no serial communications will occur. Also, once the DLL is set, at least 8 l4_sp_clk clock cycles should be allowed to pass before transmitting or receiving data.
Interrupt Enable Register:
This register may only be accessed when the DLAB bit [7] of the LCR Register is set to 0.Allows control of the Interrupt Enables for transmit and receive functions.

Module Instance	Base Address	Register Address
`i_uart_0_uart_address_block`	`0xFFC02000`	`0xFFC02004`
`i_uart_1_uart_address_block`	`0xFFC02100`	`0xFFC02104`

Size: 32

Offset: 0x4

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`rsvd_ier_dlh_31to8` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`rsvd_ier_dlh_31to8` `RO 0x0`								`ptime_dlh7` `RW 0x0`	`dlh6` `RW 0x0`	`dlh5` `RW 0x0`	`dlh4` `RW 0x0`	`edssi_dhl3` `RW 0x0`	`elsi_dhl2` `RW 0x0`	`etbei_dlhl` `RW 0x0`	`erbfi_dlh0` `RW 0x0`

ier_dlh Fields

Bit

Name

Description

Access

Reset

31:8

rsvd_ier_dlh_31to8

Reserved bits [31:8] - Read Only

RO

0x0

ptime_dlh7

Divisor Latch High Register:
Bit 7 of DLH value.
Interrupt Enable Register:
This is used to enable/disable the generation of THRE Interrupt.

Value	Description
0	disable tx-hold-reg-empty interrupt
1	enable tx-hold-reg-empty interrupt

RW

0x0

dlh6

Bit 6 of DLH value.

RW

0x0

dlh5

Bit 5 of DLH value.

RW

0x0

dlh4

Bit 4 of DLH value.

RW

0x0

edssi_dhl3

Divisor Latch High Register:
Bit 3 of DLH value.
Interrupt Enable Register:
This is used to enable/disable the generation of Modem Status Interrupts. This is the fourth highest priority interrupt.

Value	Description
0	disable modem status interrupt
1	enable modem status interrupt

RW

0x0

elsi_dhl2

Divisor Latch High Register:
Bit 2 of DLH value.
Interrupt Enable Register:
This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt.

Value	Description
0	Disable interrupt line stat
1	Enable interrupt line stat

RW

0x0

etbei_dlhl

Divisor Latch High Register:
Bit 1 of DLH value.
Interrupt Enable Register:
Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt.

Value	Description
0	Tx disable
1	Tx enable

RW

0x0

erbfi_dlh0

Divisor Latch High Register:
Bit 0 of DLH value.
Interrupt Enable Register:
Used to enable/disable the generation of the Receive Data Available Interrupt and the Character Timeout Interrupt(if FIFO's enabled). These are the second highest priority interrupts.

Value	Description
0	Interrupt Disable
1	Interrupt Enable

RW

0x0