DIEPINT10
Device IN Endpoint 10 Interrupt Register
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_usbotg_0_DWC_otg_intreg | 0xFFB00000 | 0xFFB00A48 |
| i_usbotg_1_DWC_otg_intreg | 0xFFB40000 | 0xFFB40A48 |
Size: 32
Offset: 0xA48
Access: RW
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
RESERVED RO 0x0 |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RESERVED RO 0x0 |
NYETIntrpt RW 0x0 |
NAKIntrpt RW 0x0 |
BbleErr RW 0x0 |
PktDrpSts RW 0x0 |
Reserved |
BNAIntr RW 0x0 |
TxfifoUndrn RW 0x0 |
TxFEmp RO 0x1 |
INEPNakEff RW 0x0 |
INTknEPMis RW 0x0 |
INTknTXFEmp RW 0x0 |
TimeOUT RW 0x0 |
AHBErr RW 0x0 |
EPDisbld RW 0x0 |
XferCompl RW 0x0 |
DIEPINT10 Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31:15 | RESERVED |
RESERVED |
RO | 0x0 | ||||||
| 14 | NYETIntrpt |
NYET Interrupt (NYETIntrpt) The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
|
RW | 0x0 | ||||||
| 13 | NAKIntrpt |
NAK Interrupt (NAKInterrupt) The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is transmitted due to un-availability of data in the TXFifo.
|
RW | 0x0 | ||||||
| 12 | BbleErr |
NAK Interrupt (BbleErr) The core generates this interrupt when babble is received for the endpoint.
|
RW | 0x0 | ||||||
| 11 | PktDrpSts |
Packet Drop Status (PktDrpSts) This bit indicates to the application that an ISOC OUT packet has been dropped. This bit does not have an associated mask bit and does not generate an interrupt. Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer interrupt feature is selected.
|
RW | 0x0 | ||||||
| 9 | BNAIntr |
BNA (Buffer Not Available) Interrupt (BNAIntr) This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates this interrupt when the descriptor accessed is not ready For the Core to process, such as Host busy or DMA done
|
RW | 0x0 | ||||||
| 8 | TxfifoUndrn |
Fifo Underrun (TxfifoUndrn) Applies to IN endpoints Only This bit is valid only If thresholding is enabled. The core generates this interrupt when it detects a transmit FIFO underrun condition For this endpoint.
|
RW | 0x0 | ||||||
| 7 | TxFEmp |
Transmit FIFO Empty (TxFEmp) This bit is valid only For IN Endpoints This interrupt is asserted when the TxFIFO For this endpoint is either half or completely empty. The half or completely empty status is determined by the TxFIFO Empty Level bit in the Core AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
|
RO | 0x1 | ||||||
| 6 | INEPNakEff |
IN Endpoint NAK Effective (INEPNakEff) Applies to periodic IN endpoints only. This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. This interrupt indicates that the core has sampled the NAK bit Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core. This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.
|
RW | 0x0 | ||||||
| 5 | INTknEPMis |
IN Token Received with EP Mismatch (INTknEPMis) Applies to non-periodic IN endpoints only. Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one For which the IN token was received. This interrupt is asserted on the endpoint For which the IN token was received.
|
RW | 0x0 | ||||||
| 4 | INTknTXFEmp |
IN Token Received When TxFIFO is Empty (INTknTXFEmp) Applies to non-periodic IN endpoints only. Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint For which the IN token was received.
|
RW | 0x0 | ||||||
| 3 | TimeOUT |
Timeout Condition (TimeOUT) In shared TX FIFO mode, applies to non-isochronous IN endpoints only. In dedicated FIFO mode, applies only to Control IN endpoints. In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted. Indicates that the core has detected a timeout condition on the USB For the last IN token on this endpoint.
|
RW | 0x0 | ||||||
| 2 | AHBErr |
AHB Error (AHBErr) Applies to IN and OUT endpoints. This is generated only in Internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address.
|
RW | 0x0 | ||||||
| 1 | EPDisbld |
Endpoint Disabled Interrupt (EPDisbld) Applies to IN and OUT endpoints. This bit indicates that the endpoint is disabled per the application's request.
|
RW | 0x0 | ||||||
| 0 | XferCompl |
Transfer Completed Interrupt (XferCompl) Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled - For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO. - For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit For the corresponding descriptor is Set. When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, For this endpoint.
|
RW | 0x0 |