onfi_pgm_cache_timing_mode

         Asynchronous Program Cache Timing modes supported by the connected ONFI device

Module Instance	Base Address	Register Address
`sdm_i_nand_param`	`0xFFA10300`	`0xFFA103B0`

Size: 32

Offset: 0xB0

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`										`value` `RO 0x0`

onfi_pgm_cache_timing_mode Fields

Bit	Name	Description	Access	Reset
5:0	`value`	The values in the field should be interpreted as follows[list] []Bit 0 - Supports Timing mode 0. []Bit 1 - Supports Timing mode 1. []Bit 2 - Supports Timing mode 2. []Bit 3 - Supports Timing mode 3. []Bit 4 - Supports Timing mode 4. []Bit 5 - Supports Timing mode 5.[/list]	`RO`	`0x0`

Bit

Name

Description

Access

Reset

5:0

value

The values in the field should be interpreted as follows[list]
                                  [*]Bit 0 - Supports Timing mode 0.
                                  [*]Bit 1 - Supports Timing mode 1.
                                  [*]Bit 2 - Supports Timing mode 2.
                                  [*]Bit 3 - Supports Timing mode 3.
                                  [*]Bit 4 - Supports Timing mode 4.
                                  [*]Bit 5 - Supports Timing mode 5.[/list]

RO

0x0