GHWCFG2 

         User HW Config2 Register
Module Instance Base Address Register Address
i_usbotg_0_DWC_otg_intreg 0xFFB00000 0xFFB00048
i_usbotg_1_DWC_otg_intreg 0xFFB40000 0xFFB40048

Size: 32

Offset: 0x48

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

TknQDepth

RO 0x8

PTxQDepth

RO 0x3

NPTxQDepth

RO 0x2

RESERVED

RO 0x0

MultiProcIntrpt

RO 0x0

DynFifoSizing

RO 0x1

PerioSupport

RO 0x1

NumHstChnl

RO 0xF

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NumHstChnl

RO 0xF

NumDevEps

RO 0xF

FSPhyType

RO 0x0

HSPhyType

RO 0x2

SingPnt

RO 0x0

OtgArch

RO 0x2

OtgMode

RO 0x0

GHWCFG2 Fields

Bit Name Description Access Reset
30:26 TknQDepth 
Device Mode IN Token Sequence Learning Queue Depth
(TknQDepth)
Range: 0-30
RO 0x8
25:24 PTxQDepth 
Host Mode Periodic Request Queue Depth (PTxQDepth)
 2'b00: 2
 2'b01: 4
 2'b10: 8
 2'b11:16
Value Description
0x0 Queue Depth 2
0x1 Queue Depth 4
0x2 Queue Depth 8
0x3 Queue Depth 16
RO 0x3
23:22 NPTxQDepth 
Non-periodic Request Queue Depth (NPTxQDepth)
 2'b00: 2
 2'b01: 4
 2'b10: 8
 Others: Reserved
Value Description
0x0 Queue size 2
0x1 Queue size 4
0x2 Queue size 8
RO 0x2
21 RESERVED 
RESERVED
 RO 0x0
20 MultiProcIntrpt 
Multi Processor Interrupt Enabled (MultiProcIntrpt)
 1'b0: No
 1'b1: Yes
Value Description
0x0 No Multi Processor Interrupt Enabled
0x1 Multi Processor Interrupt Enabled
RO 0x0
19 DynFifoSizing 
Dynamic FIFO Sizing Enabled (DynFifoSizing)
 1'b0: No
 1'b1: Yes
Value Description
0x0 Dynamic FIFO Sizing Disabled
0x1 Dynamic FIFO Sizing Enabled
RO 0x1
18 PerioSupport 
Periodic OUT Channels Supported in Host Mode (PerioSupport)
 1'b0: No
 1'b1: Yes
Value Description
0x0 Periodic OUT Channels is not supported in Host Mode
0x1 Periodic OUT Channels Supported in Host Mode Supported
RO 0x1
17:14 NumHstChnl 
Number of Host Channels (NumHstChnl)
Indicates the number of host channels supported by the core in
Host mode. The range of this field is 0-15: 0 specifies 1 channel,
15 specifies 16 channels.
Value Description
0xa Host Channel 11
0xb Host Channel 12
0xc Host Channel 13
0xd Host Channel 14
0xe Host Channel 15
0xf Host Channel 16
0x0 Host Channel 1
0x1 Host Channel 2
0x2 Host Channel 3
0x3 Host Channel 4
0x4 Host Channel 5
0x5 Host Channel 6
0x6 Host Channel 7
0x7 Host Channel 8
0x8 Host Channel 9
0x9 Host Channel 10
RO 0xF
13:10 NumDevEps 
Number of Device Endpoints (NumDevEps)
Indicates the number of device endpoints supported by the core
in Device mode in addition to control endpoint 0. The range of
this field is 1-15.
Value Description
0xa End point 10
0xb End point 11
0xc End point 12
0xd End point 13
0xe End point 14
0xf End point 15
0x0 End point 0
0x1 End point 1
0x2 End point 2
0x3 End point 3
0x4 End point 4
0x5 End point 5
0x6 End point 6
0x7 End point 7
0x8 End point 8
0x9 End point 9
RO 0xF
9:8 FSPhyType 
Full-Speed PHY Interface Type (FSPhyType)
 2'b00: Full-speed interface not supported
 2'b01: Dedicated full-speed interface
 2'b10: FS pins shared with UTMI+ pins
 2'b11: FS pins shared with ULPI pins
Value Description
0x0 Full-speed interface not supported
0x1 Dedicated full-speed interface is supported
0x2 FS pins shared with UTMI+ pins is supported
0x3 FS pins shared with ULPI pins is supported
RO 0x0
7:6 HSPhyType 
High-Speed PHY Interface Type (HSPhyType)
 2'b00: High-Speed interface not supported
 2'b01: UTMI+
 2'b10: ULPI
 2'b11: UTMI+ and ULPI
Value Description
0x0 High-Speed interface not supported
0x1 High Speed Interface UTMI+ is supported
0x2 High Speed Interface ULPI is supported
0x3 High Speed Interfaces UTMI+ and ULPI is supported
RO 0x2
5 SingPnt 
Point-to-Point (SingPnt)
 1'b0: Multi-point application  (hub and split support)
 1'b1: Single-point application (no hub and split support)
Value Description
0x0 Multi-point application (hub and split support)
0x1 Single-point application (no hub and split support)
RO 0x0
4:3 OtgArch 
Architecture (OtgArch)
 2'b00: Slave-Only
 2'b01: External DMA
 2'b10: Internal DMA
 Others: Reserved
Value Description
0x0 Slave Mode
0x1 External DMA Mode
0x2 Internal DMA Mode
RO 0x2
2:0 OtgMode 
Mode of Operation (OtgMode)
 3'b000: HNP- and SRP-Capable OTG (Host & Device)
 3'b001: SRP-Capable OTG (Host & Device)
 3'b010: Non-HNP and Non-SRP Capable OTG (Host &
Device)
 3'b011: SRP-Capable Device
 3'b100: Non-OTG Device
 3'b101: SRP-Capable Host
 3'b110: Non-OTG Host
 Others: Reserved
Value Description
0x0 HNP- and SRP-Capable OTG (Host and Device)
0x1 SRP-Capable OTG (Host and Device)
0x2 Non-HNP and Non-SRP Capable OTG (Host and Device)
0x3 SRP-Capable Device
0x4 Non-OTG Device
0x5 SRP-Capable Host
0x6 Non-OTG Host
RO 0x0