reg_caltiming5

Module Instance	Base Address	Register Address
`iohmc_ctrl_inst_0_iohmc_ctrl_mmr_top_inst`	`0xF8010000`	`0xF8010090`

Size: 32

Offset: 0x90

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`												`cfg_t_param_srf_to_zq_cal` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`cfg_t_param_srf_to_zq_cal` `RW 0x0`						`cfg_t_param_srf_to_valid` `RW 0x0`

reg_caltiming5 Fields

Bit	Name	Description	Access	Reset
19:10	`cfg_t_param_srf_to_zq_cal`	iohmc_ctrl_mmr_top_inst.cfg_t_param_srf_to_zq_cal[9:0] Name:Self Refresh to ZQCAL Description:Self refresh to ZQ calibration window.	`RW`	`0x0`
9:0	`cfg_t_param_srf_to_valid`	iohmc_ctrl_mmr_top_inst.cfg_t_param_srf_to_valid[9:0] Name:Self Refresh to Valid Description:Self-refresh to valid bank command window.	`RW`	`0x0`

Bit

Name

Description

Access

Reset

19:10

cfg_t_param_srf_to_zq_cal

iohmc_ctrl_mmr_top_inst.cfg_t_param_srf_to_zq_cal[9:0]
Name:Self Refresh to ZQCAL
Description:Self refresh to ZQ calibration window.

RW

0x0

9:0

cfg_t_param_srf_to_valid

iohmc_ctrl_mmr_top_inst.cfg_t_param_srf_to_valid[9:0]
Name:Self Refresh to Valid
Description:Self-refresh to valid bank command window.

RW

0x0