INTMODE 

         Interrupt modes of ECC RAM system
Module Instance Base Address Register Address
sdm_ecc_nand_w_ecc_registerBlock 0xFFA20800 0xFFA2081C

Size: 32

Offset: 0x1C

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

INTONCMP

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

INTONOVF

0x0

Reserved

INTMODE

0x0

INTMODE Fields

Bit Name Description Access Reset
16 INTONCMP 
Enable interrupt on compare.
Value Description
0 Disable interrupt on compare feature
1 Enable interrupt on compare feature
RW 0x0
8 INTONOVF 
Enable interrupt on overflow.
Value Description
0 Disable interrupt on LUT overflow
1 Enable interrupt on LUT overflow
RW 0x0
0 INTMODE 
Interrupt mode for single-bit error
Value Description
0 Enable interrupt on all error mode. Every single-bit error will cause interrupt.
1 Enable interrupt on distinct error. Every distinct error which is logged into LUT will cause interrupt.
RW 0x0