smmu_ssd_reg_0

         SSD Register 0

Note: For register and programming information, please refer to the Arm^® CoreLink™ MMU System Memory Management Unit Technical Reference Manual.

Module Instance	Base Address	Register Address
`i_aps_smmu_secure_registers`	`0xFA000000`	`0xFA004000`

Size: 32

Offset: 0x4000

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`ssd_index_8_31` `RO 0xFFFFFF`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`ssd_index_8_31` `RO 0xFFFFFF`								`ssd_index_7` `RW 0x1`	`ssd_index_6` `RW 0x1`	`ssd_index_5` `RW 0x1`	`ssd_index_4` `RW 0x1`	`ssd_index_3` `RW 0x0`	`ssd_index_2` `RW 0x0`	`ssd_index_1` `RW 0x0`	`ssd_index_0` `RW 0x0`