ddr_scheduler_cs_obs_at_main_AtbEndPoint Summary

Base Address: 0xF8021000

Register Address Offset	Bit Fields
`soc_ddr_scheduler_inst_0_cs_obs_at_main_AtbEndPoint`
`cs_obs_at_main_AtbEndPoint_Id_CoreId` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CORECHECKSUM` `RO 0xCA7CA6`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CORECHECKSUM` `RO 0xCA7CA6`								`CORETYPEID` `RO 0x7`
`cs_obs_at_main_AtbEndPoint_Id_RevisionId` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`FLEXNOCID` `RO 0x148`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`FLEXNOCID` `RO 0x148`								`USERID` `RO 0x0`
`cs_obs_at_main_AtbEndPoint_AtbId` `0x8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`									`ATBID` `RW 0x0`
`cs_obs_at_main_AtbEndPoint_AtbEn` `0xC` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`ATBEN` `RW 0x0`
`cs_obs_at_main_AtbEndPoint_SyncPeriod` `0x10` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`											`SYNCPERIOD` `RW 0x0`