flashcmd
Module Instance | Base Address | Register Address |
---|---|---|
sdm_qspi_qspiregs | 0xFF8D2000 | 0xFF8D2090 |
Size: 32
Offset: 0x90
Access: RW
Bit Fields | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
cmdopcode RW 0x0 |
enrddata RW 0x0 |
numrddatabytes RW 0x0 |
encmdaddr RW 0x0 |
enmodebit RW 0x0 |
numaddrbytes RW 0x0 |
||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
enwrdata RW 0x0 |
numwrdatabytes RW 0x0 |
numdummybytes RW 0x0 |
flash_cmd_cntrl_resv1_fld RO 0x0 |
cmdexecstat RO 0x0 |
execcmd WO 0x0 |
flashcmd Fields
Bit | Name | Description | Access | Reset | ||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31:24 | cmdopcode |
The command opcode field should be setup before triggering the command. For example, 0x20 maps to SubSector Erase. Writeing to the execute field (bit 0) of this register launches the command. NOTE : Using this approach to issue commands to the device will make use of the instruction type of the device instruction configuration register. If this field is set to 2'b00, then the command opcode, command address, command dummy bytes and command data will all be transferred in a serial fashion. If this field is set to 2'b01, then the command opcode, command address, command dummy bytes and command data will all be transferred in parallel using DQ0 and DQ1 pins. If this field is set to 2'b10, then the command opcode, command address, command dummy bytes and command data will all be transferred in parallel using DQ0, DQ1, DQ2 and DQ3 pins. |
RW | 0x0 | ||||||||||||||||||
23 | enrddata |
Set to 1 if the command specified in the command opcode field (bits 31:24) requires read data bytes to be received from the device.
|
RW | 0x0 | ||||||||||||||||||
22:20 | numrddatabytes |
Up to 8 data bytes may be read using this command. Set to 0 for 1 byte and 7 for 8 bytes.
|
RW | 0x0 | ||||||||||||||||||
19 | encmdaddr |
Set to 1 if the command specified in bits 31:24 requires an address. This should be setup before triggering the command via writing a 1 to the execute field.
|
RW | 0x0 | ||||||||||||||||||
18 | enmodebit |
Set to 1 to ensure the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes.
|
RW | 0x0 | ||||||||||||||||||
17:16 | numaddrbytes |
Set to the number of address bytes required (the address itself is programmed in the FLASH COMMAND ADDRESS REGISTERS). This should be setup before triggering the command via bit 0 of this register. 2'b00 : 1 address byte 2'b01 : 2 address bytes 2'b10 : 3 address bytes 2'b11 : 4 address bytes
|
RW | 0x0 | ||||||||||||||||||
15 | enwrdata |
Set to 1 if the command specified in the command opcode field requires write data bytes to be sent to the device.
|
RW | 0x0 | ||||||||||||||||||
14:12 | numwrdatabytes |
Up to 8 Data bytes may be written using this command Set to 0 for 1 byte, 7 for 8 bytes.
|
RW | 0x0 | ||||||||||||||||||
11:7 | numdummybytes |
Set to the number of dummy bytes required This should be setup before triggering the command via the execute field of this register. |
RW | 0x0 | ||||||||||||||||||
6:2 | flash_cmd_cntrl_resv1_fld | RO | 0x0 | |||||||||||||||||||
1 | cmdexecstat |
Command execution in progress.
|
RO | 0x0 | ||||||||||||||||||
0 | execcmd |
Execute the command.
|
WO | 0x0 |