SMMU_CB5_PMCEID

         Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation.
      
Note: For register and programming information, please refer to the Arm® CoreLink™ MMU System Memory Management Unit Technical Reference Manual.
Module Instance Base Address Register Address
i_aps_smmu_secure_registers 0xFA000000 0xFA025F20

Size: 32

Offset: 0x25F20

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Event0x12

RO 0x1

Event0x11

RO 0x1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Event0x10

RO 0x0

Reserved

Event0x0A

RO 0x1

Event0x09

RO 0x1

Event0x08

RO 0x0

Reserved

Event0x01

RO 0x1

Event0x00

RO 0x1